Solid-State Memory Voltage State Compensation for Data Retention Errors
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Solution Overview
Problem
Solid-state memory devices face decoding failures due to data retention charge loss and read disturb, which affect the ability to correctly interpret stored data over time, especially in prolonged storage and high-read utilization scenarios.
Innovation Solution
Implementing data retention and read disturb compensation methods by adjusting program voltage targets and read threshold levels in solid-state memory systems, such as NAND flash, to increase margins between voltage states, thereby reducing bit-flip errors and improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in solid-state memory cells using conventional programming methods, then the memory device can operate with standard programming voltages, but bit-flip errors occur due to data retention charge loss and read disturb over time
Solution Approach 1:
The patent applies preliminary action by adjusting programming voltage targets during the initial programming phase to compensate for anticipated charge loss and read disturb effects. By pre-positioning voltage states with increased margins before degradation occurs, the system proactively prevents bit-flip errors during data retention and repeated read operations, rather than reacting to errors after they occur.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting programming voltage targets and read threshold levels based on detected charge loss and read disturb characteristics. The system modifies these electrical parameters to increase margins between voltage states, thereby adapting the memory operation to compensate for degradation mechanisms and maintain data reliability over time.
2Reliability
If programming voltage targets are adjusted to increase margins between voltage states, then bit-flip errors are reduced, but the programming operation becomes more complex
Solution Approach 1:
The patent employs feedback by detecting actual charge loss and read disturb effects during memory operations, then using this information to adjust programming voltage targets and read threshold levels. This closed-loop approach automatically adapts the programming parameters to compensate for degradation, reducing bit-flip errors without requiring manual intervention or complex external control systems.
Solution Approach 2:
The memory system performs self-service by autonomously adjusting its own programming and read parameters based on detected degradation characteristics. The system uses internal detection mechanisms to identify charge loss and read disturb effects, then automatically modifies voltage targets and thresholds to maintain optimal performance, eliminating the need for external calibration or complex control infrastructure.
3Measurement precision
If read threshold levels are adjusted to compensate for charge loss, then data interpretation accuracy improves, but the read operation requires additional control mechanisms
Solution Approach 1:
The patent uses feedback to detect charge loss effects on stored data and automatically adjusts read threshold levels accordingly. By monitoring shifts in voltage state distributions caused by charge loss, the system dynamically repositions read thresholds to maintain accurate data interpretation, improving measurement precision without requiring manual calibration or complex external control.
Solution Approach 2:
The memory system performs self-service by autonomously adapting its read threshold levels based on detected charge loss characteristics. The system uses internal detection mechanisms to identify degradation effects and automatically adjusts read operation parameters to maintain data interpretation accuracy, eliminating the need for external calibration equipment or complex control infrastructure.
Data Source
AI summary
A data storage device includes a solid-state memory including memory cells and a controller configured to implement a data protection programming scheme by programming a first subset of the cells to a first voltage state using a first target voltage, programs a second subset to a second voltage state using a second target voltage higher than the first target voltage, programs a third subset to a third voltage state using a third target voltage higher than the second target voltage, and programs a fourth subset to a fourth voltage state using a fourth target voltage higher than the third target voltage. A difference in voltage between the fourth target voltage and the third target voltage may be greater or less than a difference in voltage between the third target voltage and the second target voltage and/or a difference in voltage between the second target voltage and the first target voltage.