Semiconductor Memory Voltage Supply Differentiation
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing cell array voltages while maintaining peripheral circuit voltages, leading to decreased write speed and reliability as integration increases and power consumption decreases.
Innovation Solution
Implementing a method where a first source voltage is applied as a cell array internal voltage and a second source voltage, higher than the first, is used as a word line drive voltage and for the global input/output line driver, allowing the same or substantially the same voltage level for both cell array and peripheral circuit voltages, with the option of generating this higher voltage internally or externally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If cell array voltage is reduced to lower power consumption, then power consumption decreases, but write speed and reliability deteriorate
Solution Approach 1:
The patent applies different voltage levels to different functional blocks: the cell array operates at a reduced first voltage level for low power consumption, while the write path circuit operates at a higher second voltage level to maintain write speed and reliability. This local differentiation of voltage quality allows each block to operate optimally for its specific function.
Solution Approach 2:
The patent segments the voltage supply system into two independent voltage domains: a first voltage for the cell array and a second voltage for the write path circuit. This segmentation allows independent optimization of power consumption in the cell array while maintaining performance in the write path circuit.
2Use of energy by moving object
If cell array voltage is reduced, then power consumption decreases, but sense amplifier drive capability weakens
Solution Approach 1:
The sense amplifier is located in the cell core circuit which operates at the higher second voltage level, providing sufficient drive capability. The cell array itself operates at the lower first voltage level for power savings. This local quality differentiation resolves the contradiction between power consumption and drive capability.
Solution Approach 2:
The cell core circuit acts as an intermediary between the low-voltage cell array and the high-voltage write path circuit. It receives the higher second voltage to power the sense amplifier, enabling it to maintain drive capability while the cell array operates at lower voltage for power efficiency.
3Speed
If threshold voltage of memory cell transistor is lowered to enable lower operating voltages, then lower voltage operation becomes possible, but write speed decreases
Solution Approach 1:
The patent changes the voltage parameter from a single uniform voltage to a multi-level voltage system. By applying a higher second voltage to the write path circuit and cell core circuit, the system achieves both low power consumption in the cell array and high write speed in the write path, without being constrained by threshold voltage limitations.
Data Source
AI summary
In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode.