Semiconductor Memory Voltage Suspension for Operation Time Reduction
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Solution Overview
Problem
Current semiconductor memory devices experience prolonged times between operations due to the recovery and boosting processes required for voltage generation, leading to increased power consumption and reduced efficiency in accessing memory cell arrays during write, read, and erase operations.
Innovation Solution
Implementing a voltage suspension mode where the internal voltage is held between operations, eliminating the need for immediate recovery and boosting, thus shortening the time between operations and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage recovery and boosting processes are performed between operations, then voltage stability is ensured, but operation time increases and power consumption rises
Solution Approach 1:
The patent applies preliminary action by performing voltage recovery and boosting processes in advance before a sequence of operations, rather than between each operation. The control circuit determines when a sequence of operations will be executed and performs the voltage preparation work once at the beginning, allowing the voltage to be maintained throughout the sequence without repeated recovery and boosting cycles.
Solution Approach 2:
The patent implements continuity of useful action by maintaining the internal voltage at an appropriate level throughout a sequence of operations without interruption. The control circuit keeps the voltage sustained between operations within the sequence, eliminating the need to drop and rebuild voltage repeatedly, thus ensuring continuous useful action without wasteful cycles of recovery and boosting.
2Reliability
If voltage recovery and boosting processes are performed between operations, then proper voltage levels are achieved, but power consumption increases
Solution Approach 1:
The control circuit performs voltage recovery and boosting once at the beginning of a determined operation sequence, preparing the voltage in advance. This preliminary action eliminates the need for repeated voltage preparation between operations, significantly reducing power consumption while ensuring proper voltage levels are achieved for all operations in the sequence.
Solution Approach 2:
The patent maintains continuous voltage supply throughout the operation sequence by avoiding repeated recovery and boosting cycles. The control circuit sustains the internal voltage at appropriate levels between operations within the sequence, eliminating energy-wasting voltage drops and rebuilds, thus reducing overall power consumption while maintaining voltage level accuracy.
3Loss of time
If internal voltage is held between operations, then operation time is reduced, but voltage control complexity increases
Solution Approach 1:
The patent applies dynamics by making the voltage control behavior adaptive based on operation sequences. The control circuit dynamically adjusts its behavior: when a sequence of operations is detected, it holds the voltage between operations; when operations are not part of a sequence, it performs traditional recovery and boosting. This dynamic adaptation reduces time between operations while managing complexity through context-aware control.
Solution Approach 2:
The control circuit uses feedback by monitoring the operation sequence determination to control voltage holding behavior. The circuit receives feedback about whether operations form a sequence and adjusts voltage control accordingly, holding voltage only when appropriate for sequence operations. This feedback mechanism enables intelligent voltage management that reduces time penalties while avoiding unnecessary complexity in non-sequence scenarios.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a control circuit, and a voltage generation circuit. The control circuit is configured to perform a first operation to access the memory cell array and then a second operation to access the memory cell array. The voltage generation circuit is configured to generate a first operation voltage, which is supplied from an output terminal of the voltage generation circuit to the memory cell array during the first operation, and a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation. The control circuit is configured to control the voltage generation circuit to maintain a voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation.