Memory Read Voltage Switching for Faster Reliable NAND Decoding
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Solution Overview
Problem
Rewritable non-volatile memory modules with severe voltage shifting have a low decoding success rate in hard bit mode decoding, leading to prolonged waiting times for data decoding in both hard and soft bit mode decoding.
Innovation Solution
A memory control method that sends a first read command sequence using a first read voltage level to obtain data, and if decoding fails, sends a second read command sequence using a different second read voltage level, using assistance information only if the second voltage level meets specific conditions and the data meets additional criteria to improve decoding success rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hard bit mode decoding is used with voltage level adjustment, then decoding speed is faster, but decoding success rate is low for memory modules with severe voltage shifting
Solution Approach 1:
The patent implements dynamic switching between hard bit mode decoding and soft bit mode decoding based on real-time decoding success rate feedback. When the decoding success rate falls below a threshold, the system transitions from fast hard bit mode to more reliable soft bit mode, resolving the contradiction between speed and reliability by making the decoding mode adaptive rather than static
Solution Approach 2:
The patent changes the decoding mode parameter dynamically based on voltage shifting conditions. By monitoring whether voltage shifting exceeds a threshold and adjusting the decoding strategy accordingly (hard bit mode for mild shifting, soft bit mode for severe shifting), the system optimizes both decoding speed and success rate under different operational conditions
2Reliability
If soft bit mode decoding is used to improve decoding success rate, then more read voltage levels are used, but decoding time increases significantly
Solution Approach 1:
The system dynamically selects between hard bit mode and soft bit mode based on real-time monitoring of decoding success rates and voltage shifting conditions. This dynamic approach ensures that soft bit mode (which takes longer but has higher success rate) is only used when necessary, while hard bit mode (which is faster) is used when conditions permit, thus minimizing time loss while maintaining high decoding success rates
Solution Approach 2:
The patent changes the decoding mode parameter based on voltage shifting thresholds. When voltage shifting is within acceptable limits, hard bit mode is used for fast decoding. When voltage shifting exceeds the threshold, the system switches to soft bit mode to ensure decoding success, thereby adapting the decoding parameters to match the actual memory conditions and avoiding unnecessary time expenditure
3Reliability
If assistance information is used in every decoding attempt, then decoding success rate improves, but system complexity and processing overhead increase
Solution Approach 1:
The patent applies assistance information partially rather than in every decoding attempt. By using assistance information only when voltage shifting exceeds the threshold or when hard bit mode decoding fails, the system achieves improved decoding success rate without the full overhead of always applying assistance information, thus balancing reliability improvement with acceptable system complexity
Data Source
AI summary
A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: sending a first read command sequence which indicates a reading of a first physical unit by using a first read voltage level to obtain first data; decoding the first data; sending a second read command sequence which indicates a reading of the first physical unit by using a second read voltage level to obtain second data; decoding the second data with assistance information to improve a decoding success rate of the second data if the second read voltage level meets a first condition or the second data meets a second condition; and decoding the second data without the assistance information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.