Memory Voltage Throttling for Stable Operation Under Power Drops

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Solution Overview

Problem

Conventional thermal throttling methods fail to prevent memory device failures due to mismatches between power systems and memory device capabilities, leading to operation failures at normal or elevated temperatures.

Innovation Solution

A performance throttling manager monitors input voltage levels to select appropriate performance levels for memory subsystems, reducing current consumption and preventing failures by adjusting performance based on voltage thresholds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If thermal throttling is used to manage memory performance, then temperature control is achieved, but memory device failures occur due to power system mismatches at normal temperatures

Engineering Contradiction:
Improvetemperature controlVSAvoidmemory device operation reliability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent changes the control parameter from temperature to input voltage level. The performance throttling manager monitors input voltage and dynamically adjusts memory subsystem performance levels based on voltage thresholds, rather than relying on temperature-based throttling that fails to prevent power system mismatches.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements feedback by continuously monitoring input voltage levels and adjusting memory performance accordingly. The performance throttling manager uses voltage threshold comparisons to trigger performance level changes, creating a closed-loop control system that responds to real-time power conditions.

Inventive Principle:
Principle #23Feedback

2Productivity

If memory subsystem operates at high performance level, then productivity is improved, but excessive current consumption causes voltage drops and operation failures

Engineering Contradiction:
Improvememory subsystem performanceVSAvoidoperation stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent makes the memory subsystem performance dynamic by introducing multiple performance levels that can be adjusted in real-time. The system transitions between performance levels based on monitored input voltage conditions, allowing optimal performance when voltage is stable and reduced performance when voltage drops occur.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system takes preliminary anti-action by proactively reducing performance levels when voltage drops are detected, preventing operation failures before they occur. The performance throttling manager monitors voltage and triggers throttling in advance to avoid the harmful effects of excessive current consumption.

Inventive Principle:
Principle #9Preliminary anti-action

3Reliability

If performance throttling is implemented based on voltage monitoring, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvememory operation reliabilityVSAvoidthrottling management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The performance throttling manager serves multiple functions: it monitors input voltage, compares voltage levels against thresholds, determines appropriate performance levels, and controls memory subsystem operation. This multi-functional approach consolidates what could be separate complex subsystems into a single management unit.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12475037B2Voltage-triggered performance throttling
Publication Date: 2025.11.18 MICRON TECHNOLOGY INC
  • US12475037B2 patent drawing
  • US12475037B2 patent drawing
  • US12475037B2 patent drawing

AI summary

Exemplary methods, apparatuses, and systems include a performance throttling manager for controlling performance levels of a memory subsystem using input voltages. The performance throttling manager monitors input voltages to a memory device to determine a current input voltage value, while the memory device is operating at a first performance level. The performance throttling manager detects that the current input voltage value satisfies a threshold voltage value. The performance throttling manager selects a second performance level that is lower than the first performance level and throttles the performance of the memory device in response to detecting that the current input voltage value satisfies a threshold voltage value.