Memory Device Voltage Timing Control
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Solution Overview
Problem
Current memory devices face challenges in synchronizing the timing of voltage supply to word lines and bit lines, leading to potential forward bias in PN junctions and increased circuit complexity, which affects reliability and operation efficiency.
Innovation Solution
The memory device employs a configuration with multiple power source domains to independently control word lines and bit lines, using level shifters and delay circuits to synchronize voltage supply timing and prevent forward bias, thereby simplifying circuit design and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage supply timing is not synchronized between word lines and bit lines, then operational simplicity is maintained, but forward bias occurs in PN junctions and reliability deteriorates
Solution Approach 1:
The memory device is divided into multiple power source domains, with each domain independently controlling voltage supply to specific interconnects (word lines or bit lines). This segmentation enables precise timing control of voltage supply to different lines, preventing forward bias in PN junctions while maintaining operational reliability without requiring complex global synchronization circuitry.
2Reliability
If multiple power source domains are implemented to independently control voltage supply, then timing synchronization is achieved and reliability improves, but device complexity increases
Solution Approach 1:
The power source control is segmented into multiple independent domains, where each domain manages voltage supply to specific interconnects. This segmentation allows straightforward implementation of timing control within each domain without requiring complex inter-domain coordination, thus improving reliability while keeping the overall circuit design manageable.
Solution Approach 2:
Voltage supply to word lines and bit lines is controlled to occur in predetermined sequences through the multiple power source domains. By preliminarily establishing the timing relationship between voltage supplies to different interconnects, the design prevents forward bias conditions without requiring complex real-time synchronization mechanisms.
3Adaptability or versatility
If voltage supply timing is delayed without proper synchronization, then operational flexibility is maintained, but timing lag causes forward bias and operational errors
Solution Approach 1:
The power source control is divided into multiple independent domains that can be configured to supply voltage to different interconnects with controlled timing. This segmentation maintains operational flexibility by allowing independent timing adjustment for each domain while preventing forward bias through proper sequencing of voltage supply.
Solution Approach 2:
The timing relationships between voltage supply to different interconnects are preliminarily established through the multiple power source domains. This preliminary timing control ensures that voltage is supplied in the correct sequence, preventing forward bias in PN junctions while maintaining the flexibility to adjust timing parameters as needed.
Data Source
AI summary
According to one embodiment, a device includes: a memory cell between the first and second interconnects; a first circuit in a domain having a range of a first voltage to a second voltage higher than the first voltage, the first circuit controlling supply of the second voltage to the first interconnect; a second circuit in a domain having a range of a third voltage lower than the first voltage to the first voltage, the second circuit controlling supply of the third voltage to the second interconnect; and a third circuit in a domain having a range of a fourth voltage lower than the first voltage to a fifth voltage higher than the first voltage, the third circuit controlling supply of a sixth voltage to the first and second interconnects.