Semiconductor Memory Voltage Control Data Transfer Unit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing NAND flash memory devices require complex voltage control systems to manage different voltages for various operations, leading to increased chip area due to the need for numerous interconnect lines and large flip-flop circuits for data transfer.
Innovation Solution
A semiconductor memory device with a voltage control data transfer unit that uses latch circuits to hold and output voltage control data, reducing the number of interconnect lines and chip area by shifting an enable signal to manage voltage control data transfer serially.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip-flop circuits are used to transfer voltage control data to each word line, then voltage control functionality is achieved, but chip area increases due to large circuit size and numerous interconnect lines
Solution Approach 1:
The patent divides the voltage control data transfer system into multiple transfer circuits, each responsible for a specific word line. Each transfer circuit contains a latch circuit that can be independently controlled by an enable signal, allowing segmented control of voltage application to different word lines while reducing the overall circuit complexity compared to using full flip-flop circuits for each line.
Solution Approach 2:
The patent merges the data holding function and the transfer control function into a single latch circuit structure. The latch circuit combines the data input, data output, and enable signal response in one integrated unit, eliminating the need for separate control logic and interconnect lines that would be required if flip-flop circuits were used for each word line.
2Productivity
If multiple voltages are applied to different word lines at different timings for write operations, then write characteristics improve, but device complexity increases due to numerous control signals required
Solution Approach 1:
The patent implements dynamic voltage control where the enable signal can be selectively activated for different transfer circuits at different timings. This allows the system to dynamically apply different voltages to different word lines based on the specific operation requirements, enabling improved write characteristics while maintaining manageable control complexity through the shared latch circuit architecture.
Solution Approach 2:
The patent applies different voltages to different word lines based on their specific requirements during write operations. Each transfer circuit can receive and hold different voltage control data tailored to its corresponding word line, allowing localized optimization of voltage application while using a unified control mechanism through the enable signal.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to generate voltages required for operations of the memory cell array, selection circuits connected to the word lines, respectively, each of the selection circuits being configured to select a voltage applied to a word line from the voltages, and a transfer unit configured to transfer items of control data for selecting the voltage to the selection circuits, respectively. The transfer unit includes transfer circuits which shift an enable signal in sequence. The transfer circuits include latch circuits which hold the items of control data based on the shifted enable signal, respectively.