Memory Device Voltage Transition Data Latching

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in preventing data and internal write clock misalignment during voltage transitions between different operational modes, which can lead to errors and undesirable downtimes.

Innovation Solution

The memory device operates in a single data rate mode during voltage transitions, latching incoming data on either the rising or falling edge of the internal write clock signal, thereby reducing the likelihood of misalignment. Once the voltage stabilizes, the device returns to a double data rate mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the memory device operates in double data rate mode during voltage transitions, then data throughput is maximized, but data and clock misalignment errors occur

Engineering Contradiction:

Improvedata throughputVSAvoiddata and clock alignment

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system dynamically switches between double data rate mode (for normal operation) and single data rate mode (during voltage transitions). The mode register write command triggers a transition to single data rate mode when voltage changes are detected, then automatically returns to double data rate mode when voltage stabilizes, optimizing both throughput and reliability under different conditions

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the data latching parameter from double data rate (latching on both rising and falling edges) to single data rate (latching on only one edge) during voltage transitions. This parameter change reduces the likelihood of misalignment between data and internal write clock while maintaining operational continuity

Inventive Principle:

Principle #35Parameter changes

2Reliability

If access operations are suspended during voltage transitions, then data and clock misalignment is prevented, but downtime increases

Engineering Contradiction:

Improvedata and clock alignmentVSAvoidaccess downtime

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent enables continuous access operations during voltage transitions by switching to single data rate mode rather than suspending operations. Data can continue to be latched on the stable edge of the clock signal even as voltage transitions, eliminating downtime while maintaining alignment through the simplified latching mechanism

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The system proactively switches to single data rate mode upon detecting a voltage transition (via mode register write command) before misalignment can occur. This preliminary action prevents potential errors while maintaining continuous operation, then automatically returns to double data rate mode when voltage stabilizes

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250191640A1Apparatuses and methods for access operations during voltage transition

Publication Date: 2025.06.12 MICRON TECHNOLOGY INC

AI summary

Apparatuses, systems, and methods for access operations during a voltage transition. A memory may receive a system voltage and a clock signal from a controller. The controller may be used to time operations such as write operations however, an internal clock signal of the memory may be dependent on the voltage. The memory operates at a double data rate relative to the clock signal. During a transition period while the voltage changes between levels, the memory may switch to a transition mode where the memory operates at a single data rate.