Nonvolatile Memory Device Voltage Uniformity Control

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Solution Overview

Problem

In nonvolatile memory devices, the uneven supply of program voltage due to delay times results in varying threshold voltages among memory cells, affecting the reliability of the device.

Innovation Solution

A control unit is introduced to adjust and equalize the time period for program voltage supply to each memory cell by generating correction voltages based on the distance from the row decoder, ensuring uniform voltage levels across all memory cells during programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If program voltage is supplied to all memory cells simultaneously, then programming operation can be performed, but memory cells at different distances from the row decoder experience different delay times resulting in non-uniform threshold voltages

Engineering Contradiction:
Improveuniformity of threshold voltageVSAvoidprogram operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-charging bit lines to a specific voltage level before the program voltage is applied to the word line. This pre-charging action compensates for the delay time that will occur during program voltage propagation, ensuring that memory cells at different distances from the row decoder receive the effective program voltage at the same time, thus achieving uniform threshold voltage distribution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements local quality by applying different pre-charge voltages to different groups of bit lines based on their distance from the row decoder. Memory cells are divided into multiple groups, and each group receives a tailored pre-charge voltage that compensates for its specific delay characteristics, ensuring that all memory cells across the array achieve uniform programming timing despite their different physical locations.

Inventive Principle:
Principle #3Local quality

2Reliability

If memory cells are divided into multiple groups with different pre-charge voltages, then uniform threshold voltage can be achieved, but device complexity increases

Engineering Contradiction:
Improveuniformity of threshold voltageVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the memory cell array into multiple groups based on their distance from the row decoder. Each group is assigned a specific pre-charge voltage level, allowing independent control of the timing characteristics for each segment. This segmentation enables precise compensation for delay variations while maintaining a manageable control structure through group-based management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements parameter changes by varying the pre-charge voltage parameter across different bit line groups. Instead of using a single uniform pre-charge voltage, the system adjusts the voltage parameter according to the distance from the row decoder, creating a gradient of pre-charge voltages that compensates for delay variations. This parameter-based approach provides flexibility in timing control without requiring complex circuit modifications.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8363471B2Nonvolatile memory device and method of programming the same
Publication Date: 2013.01.29 SK HYNIX INC
  • US8363471B2 patent drawing
  • US8363471B2 patent drawing
  • US8363471B2 patent drawing

AI summary

A nonvolatile memory device and a method of programming the device includes a memory cell array configured to have a number of memory cells, a row decoder coupled to the memory cells through word lines, page buffers coupled to the memory cells through bit lines, and a control unit configured to output correction voltages for reducing a difference in voltage between a selected one of the word lines and a channel region of a selected one of the memory cells in response to a program operation being performed.