3D Memory Read Voltage Calibration for Temperature and Wear Drift
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Solution Overview
Problem
In three-dimensional memory devices, read voltage offsets occur due to temperature changes and wear, leading to data reading errors, which existing technologies fail to adequately address.
Innovation Solution
A method and apparatus for voltage calibration that involves detecting the target temperature and performing read operations at multiple candidate times to determine a target read voltage offset parameter, using a stored offset function to calibrate the read voltage and compensate for temperature and time variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read voltage is applied without calibration, then reading operation can be performed, but read voltage accuracy deteriorates due to temperature changes and wear
Solution Approach 1:
The patent performs preliminary calibration operations to determine offset parameters before actual data reading. The system pre-determines read voltage offset parameters by conducting calibration reads at different voltages and times, then applies these pre-calculated offsets to compensate for temperature and wear effects during normal operation, ensuring accurate readings without real-time iteration.
Solution Approach 2:
The patent implements feedback mechanisms where read fail bits are detected and used to adjust subsequent read operations. The system monitors reading results, identifies failures caused by voltage offsets, and uses this feedback to refine offset parameter selections, creating a closed-loop system that continuously improves reading accuracy based on actual performance.
2Measurement precision
If multiple calibration parameters are used to compensate for temperature and time variations, then read voltage accuracy improves, but device complexity increases
Solution Approach 1:
The patent segments the calibration process into distinct components: temperature compensation parameters, time offset parameters, and read voltage offset parameters. Each parameter type addresses a specific source of error independently, allowing the system to manage complexity by breaking down the overall calibration task into manageable, specialized sub-tasks rather than attempting a monolithic calibration approach.
Solution Approach 2:
The patent systematically varies calibration parameters such as read voltage levels, read time intervals, and temperature conditions to determine optimal offset values. By changing these parameters in controlled ways during calibration and selecting combinations that minimize read failures, the system achieves high accuracy while keeping the actual reading operation simple through parameter lookup rather than complex real-time calculations.
3Measurement precision
If calibration operations are performed at multiple candidate times, then temperature-related voltage offsets are compensated, but time consumption increases
Solution Approach 1:
The patent performs calibration reads at multiple candidate times and voltage levels, which is more extensive than a single calibration point. However, it selects only the necessary offset parameters from this comprehensive set based on which combination produces the minimum number of read fail bits, avoiding the need to use all collected data and thus reducing overall calibration time while maintaining high accuracy.
Data Source
AI summary
According to one aspect of the present disclosure, a method of voltage calibration is provided. The method may include detecting a target temperature of a memory cell array. The method may include performing a read operation on the memory cell array at each of multiple candidate times with a standard read voltage. The method may include obtaining a number of target read fail bits. Each of the candidate times may correspond to one of the number of the target read fail bits. The method may include determining a target read voltage offset parameter according to the target temperature, the number of the target read fail bits, the candidate time, and a stored target offset function. The method may include calibrating the read voltage of the read operation on the memory cell array with the target read voltage offset parameter.


