Memory Voltage Window Calibration for Soft Bit Read Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory systems face inefficiencies in reading data from memory cells due to shifts in optimized threshold voltages caused by factors like charge loss and temperature changes, leading to high bit error rates and prolonged retry processes for error correction.
Innovation Solution
A memory subsystem that calibrates a voltage window based on signal and noise characteristics of memory cells, using optimized read voltages to read both hard and soft bit data, thereby improving decoding efficiency and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fixed voltage windows are used for reading memory cells, then device complexity is reduced, but bit error rate increases due to voltage shifts from charge loss and temperature changes
Solution Approach 1:
The system performs preliminary calibration by measuring signal and noise characteristics at multiple test voltages before actual data reading. This preliminary characterization of the memory cell distribution enables dynamic voltage window adjustment during operation, resolving the contradiction by preparing voltage compensation data in advance without adding complexity to the main read path
Solution Approach 2:
The patent implements dynamic voltage window adjustment based on measured signal and noise characteristics. Instead of using fixed voltage windows, the system adapts the voltage window parameters (center voltage and width) according to the actual memory cell distribution and noise conditions, thereby maintaining low bit error rates under varying temperature and charge loss conditions
2Measurement precision
If multiple calibration cycles are performed to account for voltage shifts, then reading accuracy improves, but latency increases due to prolonged retry processes
Solution Approach 1:
The system performs comprehensive signal and noise characteristic measurements at multiple test voltages during an initial calibration phase. This preliminary characterization captures the memory cell distribution and noise properties, enabling the system to predict optimal voltage windows for subsequent reads without requiring repeated calibration cycles, thus reducing latency while maintaining accuracy
Solution Approach 2:
The system uses measured signal and noise characteristics as feedback to dynamically adjust voltage window parameters. By continuously monitoring the actual memory cell distribution and adapting the read voltage accordingly, the system achieves high reading accuracy without needing multiple trial-and-error calibration cycles, thereby reducing the time penalty
3Productivity
If voltage windows are optimized for specific conditions, then reading efficiency improves, but adaptability to different temperature and charge states deteriorates
Solution Approach 1:
The patent implements dynamic voltage window adjustment based on measured signal and noise characteristics. Instead of using fixed voltage windows, the system adapts the voltage window parameters (center voltage and width) according to the actual memory cell distribution and noise conditions, thereby maintaining low bit error rates under varying temperature and charge loss conditions
Solution Approach 2:
The system changes the parameters of the voltage window (center voltage, width, and shape) based on measured signal and noise characteristics at different test voltages. By adjusting these parameters to match the actual memory cell distribution under different operating conditions, the system maintains high reading efficiency across varying temperatures and charge states
Data Source
AI summary
A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.