Memory Input First-Stage Circuit With VREF Clock Noise Filtering
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Solution Overview
Problem
High-frequency noise from the operating clock in semiconductor memory devices, particularly in DRAM chips, is transmitted through common wiring, causing malfunctions due to the low tolerance of reference voltage signals for noise, which existing filters are ineffective in addressing.
Innovation Solution
A semiconductor memory device with a low-pass filter connected to the input terminal to eliminate high-frequency noise components, ensuring the reference voltage remains a DC component, and the logic level is determined accurately without noise, using either passive or active low-pass filters with specific attenuation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional filter (resistor and capacitor) is provided at the input side to avoid EMC problems, then electromagnetic compatibility is improved, but it is not effective in preventing malfunction due to VREF signal noise requiring high accuracy
Solution Approach 1:
The filter circuit is segmented into multiple stages: a first low-pass filter (RC circuit) for high-frequency noise suppression and a second low-pass filter for additional noise attenuation. This multi-stage segmentation allows each filter to target specific frequency ranges, effectively preventing malfunction while preserving signal accuracy for logic level determination.
Solution Approach 2:
The patent applies different filter characteristics to different parts of the signal processing path. The first low-pass filter uses specific resistance and capacitance values optimized for high-frequency noise near the operating clock frequency, while the second filter provides additional attenuation. This local optimization ensures malfunction prevention without degrading the VREF signal quality needed for accurate logic level determination.
2Speed
If high-frequency noise occurs due to operating clock in a DRAM chip, then operation speed is improved, but noise is transmitted to other DRAM chips through common wiring causing malfunction
Solution Approach 1:
The patent extracts and removes high-frequency noise components from the VREF signal using low-pass filters before the noise can be transmitted through common wiring to other DRAM chips. By taking out the harmful high-frequency components while preserving the DC reference voltage, the system maintains high operation speeds without noise transmission to adjacent chips.
Solution Approach 2:
The patent converts the harmful high-frequency noise generated by the operating clock into a beneficial filtering opportunity. By deliberately designing low-pass filters with cutoff frequencies below the operating clock frequency, the system uses the presence of noise to drive the filtering mechanism, effectively suppressing noise transmission while maintaining the necessary reference voltage for high-speed operation.
3Object-affected harmful factors
If a low-pass filter is placed immediately near the input terminal to eliminate high-frequency noise components, then noise attenuation is improved, but the reference voltage must be maintained as a DC component
Solution Approach 1:
The patent carefully selects and adjusts the parameters (resistance and capacitance values) of the low-pass filters to achieve the desired cutoff frequency that is below the operating clock frequency but above DC. This parameter optimization allows effective high-frequency noise elimination while ensuring the DC reference voltage component passes through unchanged, maintaining signal stability for accurate logic level determination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively prevents malfunctions by reliably attenuating noise near the operating clock frequency, maintaining accurate logic level determination and reducing noise interference between DRAM chips in a memory module.
Implementation Method 1
a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components
Implementation Method 2
the low-pass filter has a predetermined attenuation amount at least at a frequency of an operating clock
Data Source
AI summary
A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.