Memory Block VT Refresh Scans for Lower Read Error Rates
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Solution Overview
Problem
Memory cells in non-volatile configurations experience degradation over time, leading to a shift from a transient threshold voltage state to a stable state with higher bit error rates, causing increased read errors and latency in memory systems.
Innovation Solution
Proactively setting memory blocks to a transient threshold voltage state by periodically applying a read voltage, either simultaneously or one at a time, to maintain them in a programmable state and reduce bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are left in stable voltage state for extended periods, then non-volatile storage is achieved, but bit error rate increases and read accuracy deteriorates
Solution Approach 1:
The patent implements periodic background scans that periodically apply read voltages to memory blocks to refresh their voltage states. This periodic intervention prevents the voltage drift that occurs during extended idle periods, thereby maintaining read accuracy without requiring continuous access to memory cells.
Solution Approach 2:
The patent performs preliminary background scans to proactively refresh memory block voltage states before they degrade to error-prone levels. By detecting and refreshing blocks that have been idle for threshold durations, the system prevents bit errors before they occur, rather than waiting for errors to manifest during read operations.
2Reliability
If background scans are performed frequently to maintain transient voltage state, then bit error rate decreases, but system latency and power consumption increase
Solution Approach 1:
The patent applies background scans selectively to individual memory blocks based on their specific idle duration and voltage state characteristics, rather than uniformly scanning all blocks. This localized approach refreshes only the blocks that need it, reducing overall scan latency and power consumption while maintaining bit error rate performance.
Solution Approach 2:
The patent dynamically adjusts background scan parameters such as scan intervals and voltage levels based on memory block usage patterns and observed voltage drift characteristics. By optimizing these parameters, the system achieves acceptable bit error rates with reduced scan frequency, thereby minimizing latency and power consumption.
3Productivity
If read voltage is applied to all memory blocks simultaneously, then voltage state refresh is efficient, but power consumption and access conflict increase
Solution Approach 1:
The patent divides the memory array into multiple banks or blocks and performs background scans on subsets of these blocks in sequential batches rather than simultaneously. This segmentation allows the system to refresh memory efficiently while spreading power consumption over time and avoiding conflicts with ongoing read/write operations on other blocks.
Data Source
AI summary
Methods, systems, and devices for transient threshold voltage scan are described. For example, a memory system may set or maintain one or more memory blocks in a transient voltage threshold (VT) state by periodically applying a read voltage to sets of one or more memory blocks in the memory system. The memory system may apply the read voltage to a set of memory blocks simultaneously using a ganged reset read (GRR). In some examples, the memory system may reset a block range (e.g., across all memory blocks of the memory system) by periodically applying the read voltage to sets of memory blocks over time to maintain the memory blocks in the transient VT state and to reduce a bit error rate associated with a stable VT state to which the memory blocks may transition if they are not reset within a threshold duration.