3D Memory Wafer Bonding Layout for Shorter Bias Paths
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Solution Overview
Problem
The integration and operational reliability of three-dimensional semiconductor devices are limited by the area occupied by unit memory cells, necessitating innovative structures and manufacturing methods to enhance memory cell stacking and peripheral circuit configurations.
Innovation Solution
A semiconductor device structure comprising multiple wafers with distinct configurations, including inverted step structures, pass transistors, page buffers, and peripheral circuits, which are bonded together to optimize memory cell array operations and reduce bias transmission paths, allowing for improved memory cell integration and data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three dimensions to improve integration, then the degree of integration is improved, but the operational reliability deteriorates due to longer bias transmission paths
Solution Approach 1:
The semiconductor device is divided into multiple wafers (first wafer with memory cell array, second wafer with pass transistors, third wafer with page buffer) bonded together. This segmentation allows each wafer to have a specialized function and reduces the bias transmission path length within each wafer, thereby maintaining operational reliability while achieving high integration through vertical stacking of multiple wafers.
Solution Approach 2:
The invention transitions from planar integration to three-dimensional wafer stacking. By bonding multiple wafers vertically, the device achieves higher integration density in the vertical dimension while keeping each individual wafer's circuit paths relatively short, thus resolving the contradiction between integration and reliability.
2Quantity of substance
If more memory cells are packed on a single wafer to improve integration, then the degree of integration is improved, but the area occupied by unit memory cells increases
Solution Approach 1:
Instead of increasing the area of unit memory cells on a single wafer, the invention stacks multiple wafers vertically to achieve higher integration. This dimensional transition allows more memory cells to be packed by utilizing the vertical space, thereby improving integration without increasing the planar area occupied by each unit memory cell.
3Productivity
If peripheral circuits are integrated on the same wafer as memory cells to improve operational efficiency, then the bias transmission path is reduced, but the area occupied by the device increases
Solution Approach 1:
Peripheral circuits are segmented from the memory cell array and placed on separate wafers. The first wafer contains the memory cell array, while the second and third wafers contain pass transistors and page buffer respectively. This segmentation reduces the area occupied on each individual wafer while maintaining operational efficiency through vertical stacking and reduced bias transmission paths.
Solution Approach 2:
Instead of expanding peripheral circuits horizontally on the same wafer as memory cells, the invention places them on vertically stacked wafers. This approach reduces the planar area occupied by the device while improving operational efficiency through shorter bias transmission paths within each wafer layer.
Data Source
AI summary
A semiconductor device may include: a first semiconductor structure including a stack including an inverted step structure, a source structure located below the stack, a bit line located above the stack, and channel structures extending through the stack; a second semiconductor structure bonded to the first semiconductor structure and including pass transistors located to face the inverted step structure and a first peripheral circuit located to face the source structure; and a third semiconductor structure bonded to the first semiconductor structure and including a page buffer located to face the bit line and a second peripheral circuit located to face the inverted step structure.