Front-to-Front Memory Wafer Stacking to Protect Logic Yield
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Solution Overview
Problem
The heterogeneous wafer-on-wafer stacking technique for high-performance computing faces challenges in improving the yield rate due to the physical stress and damage incurred during the bonding and thinning processes, particularly affecting the costly logic semiconductor structure.
Innovation Solution
The semiconductor device employs a memory stacking pair structure where memory semiconductor structures are bonded in a front-to-front manner, allowing the logic semiconductor structure to be integrated in a later stage, thereby minimizing exposure to physical stress and reducing yield impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If heterogeneous wafer-on-wafer stacking technique is implemented to stack multiple memory wafers on a logic wafer, then memory bandwidth is improved, but yield rate deteriorates due to physical stress and damage during bonding and thinning processes
Solution Approach 1:
The patent applies preliminary action by bonding memory wafers to each other first to form memory stacking pairs before integrating them with the logic wafer. This sequence protects the logic wafer from physical stress during bonding and eliminates the need for thinning memory wafers, thereby maintaining high yield rates while achieving the desired memory bandwidth through stacked memory structures.
Solution Approach 2:
The patent segments the stacking process into distinct phases: first bonding memory wafers to form pairs, then integrating these pairs with the logic wafer. This segmentation allows each bonding operation to be optimized independently and reduces the cumulative stress on any single component, particularly protecting the valuable logic wafer from damage.
2Ease of manufacture
If memory wafers are thinned during the stacking process, then integration with logic wafer is improved, but manufacturing cost increases and yield rate deteriorates
Solution Approach 1:
The patent performs the bonding action preliminarily by joining memory wafers together before logic wafer integration, which eliminates the need for subsequent thinning operations. This preliminary bonding enables direct integration at full thickness, simplifying the manufacturing process while avoiding yield losses associated with thinning delicate memory structures.
3Productivity
If logic wafer is exposed during bonding and thinning processes, then stacking is completed, but physical stress and damage occur reducing yield rate
Solution Approach 1:
The patent executes preliminary bonding between memory wafers before logic wafer integration, completing the memory stacking portion while the logic wafer remains protected. This preliminary action allows the memory structures to be fully prepared and tested before being combined with logic, ensuring productivity while protecting the logic wafer from stress and damage.
Solution Approach 2:
The patent uses already-bonded memory stacking pairs as intermediaries between the bonding process and logic wafer integration. These pre-formed pairs act as protective units that can be handled and positioned without exposing individual memory wafers to stress, thereby protecting the logic wafer while enabling complete stacking.
Data Source
AI summary
The present application discloses a semiconductor device. The semiconductor device includes a memory stacking pair. The memory stacking pair includes a first memory semiconductor structure and a second memory semiconductor structure. The first memory semiconductor structure has a first front side and a first back side opposite to the first front side. The second memory semiconductor structure has a second front side and a second back side opposite to the second front side. The first memory semiconductor structure is bonded to the second memory semiconductor structure, and the first front side of the first memory semiconductor structure is proximal to the second front side of the second memory semiconductor structure, and the first back side is distal to the second back side.