Memory Wake-Up Sequencing for Lower SRAM In-Rush Current
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Solution Overview
Problem
Existing memory devices face challenges in managing power states efficiently, particularly during transitions from sleep modes to active states, leading to high in-rush currents due to overlapping memory array power-up and bit line pre-charge operations.
Innovation Solution
Implementing a secondary sleep loop in semiconductor memory systems to separate memory array power-up and bit line pre-charge operations, reducing wake-up peak current by staging these processes sequentially.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory array power-up and bit line pre-charge operations are performed simultaneously, then wake-up time is reduced, but in-rush current increases significantly
Solution Approach 1:
The patent divides the wake-up operation into two separate sequential operations: first the memory array power-up operation, then the bit line pre-charge operation. This segmentation prevents simultaneous operation of power-intensive circuits, thereby reducing in-rush current while maintaining acceptable wake-up time through optimized sequencing
2Power
If memory array power-up and bit line pre-charge operations are performed sequentially, then in-rush current is reduced, but wake-up time increases
Solution Approach 1:
The patent performs preliminary actions by first completing the memory array power-up operation and stabilizing the array before initiating the bit line pre-charge operation. This preliminary sequencing ensures that when the second operation begins, the first operation is already complete, optimizing the overall wake-up time while maintaining current reduction benefits
Data Source
AI summary
Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a first memory cell, a first buffer, first logic circuitry, and first switching circuitry. The first memory cell may be configured to pre-charge in response to receiving a primary sleep signal. The first buffer may be configured to receive the primary sleep signal, generate a delayed primary sleep signal, and provide the delayed primary sleep signal to a second memory cell. The first logic circuitry may be configured to generate a first bit line pre-charge signal for the first memory cell of the plurality of memory cells in response to a looped sleep signal, wherein the looped sleep signal is generated based on the delayed primary sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal.