Multiprocessor Memory Watch Unit for Access Monitoring

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Solution Overview

Problem

In multiprocessor systems, managing complex memory access and debugging is challenging due to frequent memory recycling and potential unexpected interactions, which can lead to operational failures and make system verification difficult, especially during development and in field deployments.

Innovation Solution

A hardware memory watch unit is introduced to monitor and manage memory accesses by generating rules for memory access control, detecting violations, and triggering warnings or interrupts to ensure proper memory usage, integrated with a sequence processor and processing elements to enforce memory policies dynamically.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory is frequently recycled to minimize size, then memory utilization efficiency is improved, but debugging and verification of the system becomes extremely difficult

Engineering Contradiction:
Improvememory utilization efficiencyVSAvoiddebugging difficulty
Core Design Contradiction:
ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

A memory watch unit is introduced as an intermediary component between the processing elements and the memory system. This unit monitors memory accesses, tracks memory recycling operations, and provides verification capabilities without interfering with the efficient memory recycling process. The watch unit acts as a mediator that enables debugging while preserving the performance benefits of frequent memory recycling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple processing elements access memory simultaneously, then system processing capability is improved, but access control complexity and potential failures increase

Engineering Contradiction:
Improvesystem processing capabilityVSAvoidaccess control complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory watch unit implements feedback mechanisms by monitoring memory access patterns from multiple processing elements and generating status information about access violations, conflicts, or errors. This feedback enables the system to detect and manage access control issues automatically, reducing the complexity of manual access control management while maintaining high processing capability.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If software is loaded and updated in the field to support multiple air interface modes, then system adaptability is improved, but unexpected interactions and operational failures increase

Engineering Contradiction:
Improvesystem adaptabilityVSAvoidsystem reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The memory watch unit performs preliminary monitoring and verification of memory access patterns before operational failures can occur. By continuously tracking memory accesses during software updates and field operations, the system can detect potential conflicts or violations early, preventing unexpected interactions and maintaining reliability while preserving adaptability to multiple air interface modes.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9600422B2Monitoring accesses to memory in a multiprocessor system
Publication Date: 2017.03.21 U-BLOX
  • US9600422B2 patent drawing
  • US9600422B2 patent drawing
  • US9600422B2 patent drawing

AI summary

Embodiments of the present invention provide methods and apparatus in a multiprocessor system, whereby a set of rules relating to memory access are created and implemented in a hardware element. The rules can be updated dynamically, for example by the sequence processor (or sequencer) used to control the multiple processing elements.