Semiconductor Memory Weak Cell Detection via Dynamic Noise
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Solution Overview
Problem
Existing semiconductor memory devices fail to detect weak cells during the wafer level test, leading to chip failures and reduced package yield due to undetected charge sharing issues, especially as chip density increases and operation voltage decreases.
Innovation Solution
A semiconductor memory device and method utilizing a word line driving circuit that supplies a boosted voltage during active operation and a lower voltage during standby, with a weak cell detection circuit that increases noise introduction into the cell plate node during testing to identify weak cells without a separate driving circuit, thereby enhancing detection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate driving circuit is added to increase noise levels for weak cell detection, then detection capability is improved, but device complexity and area increase
Solution Approach 1:
The existing word line driving circuit is designed to perform both its normal driving function and the additional function of generating noise for weak cell detection. By configuring the driving circuit to operate in different modes (normal mode and test mode), the same hardware infrastructure serves dual purposes, eliminating the need for a separate dedicated noise generation circuit and thereby avoiding increased device complexity.
Solution Approach 2:
The word line driving circuit generates its own noise signal internally during test mode operation without requiring external noise generation hardware. The circuit uses its existing components (word lines, bit lines, memory cells) to create the necessary noise conditions for weak cell detection, making the system self-sufficient and avoiding additional circuitry.
2Use of energy by moving object
If voltage is lowered during wafer level test, then power consumption is reduced, but weak cells with charge sharing issues cannot be detected
Solution Approach 1:
The system dynamically adjusts its operating mode based on the test requirements. During normal operation, the device runs at standard voltages. During weak cell detection tests, the system transitions to a special test mode where the word line driving circuit generates controlled noise while operating at lowered voltages. This dynamic switching allows the system to maintain low power consumption during most operations while enabling weak cell detection when needed.
Solution Approach 2:
The weak cell detection is performed periodically or on-demand through test mode activation rather than continuously at high voltage. The system alternates between normal low-power operation and test mode operation, where the test mode temporarily introduces noise generation to detect weak cells, then returns to normal operation. This periodic testing approach maintains overall low power consumption while enabling detection capability.
3Measurement precision
If noise level is increased during testing, then weak cells are detected, but signal integrity during normal operation may be affected
Solution Approach 1:
The noise generation is dynamically activated only during test mode and deactivated during normal operation. The word line driving circuit switches between a test configuration (where noise is generated for detection) and a normal configuration (where signal integrity is maintained). This dynamic switching ensures that high noise levels are present only when needed for weak cell detection and absent during normal reliable operation.
Solution Approach 2:
The noise generation function is extracted as a separate, controllable mode of operation rather than being permanently integrated into the normal signal path. By isolating the noise generation to a specific test mode that can be independently activated and deactivated, the system can introduce noise for detection purposes without it interfering with normal signal integrity during regular operation.
Data Source
AI summary
A semiconductor memory device may include: a memory cell array coupled between a plurality of word lines and a plurality of bit lines; a first source voltage supply unit suitable for providing a boosted voltage to a source voltage terminal when a cell mat signal is activated; a second source voltage supply unit suitable for providing a dropped voltage that is lower than the boosted voltage to the source voltage terminal; a word line driving circuit suitable for selecting one of the plurality of word lines in response to an address combination signal and driving the selected word line and unselected word lines, when the cell mat signal is activated; and a weak cell detection circuit suitable for detecting a weak cell by checking data values of memory cells coupled to a word line which is driven by the word line driving circuit during the test mode.