Semiconductor Memory Weak Cell Information Transfer Circuit
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Solution Overview
Problem
Semiconductor memory devices face challenges in detecting and screening weak cells, which can lead to data loss and reduced reliability due to the high density of memory cells and the need for accurate testing to prevent errors and yield deterioration.
Innovation Solution
A semiconductor memory device with a weak cell control circuit and information transfer control circuit that transfers weak cell information from a non-volatile memory to a memory cell region, allowing for storage and optional refresh operations, reducing the area required for storage circuits and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If weak cell information is stored in a dedicated storage circuit, then reliability is improved, but chip area is increased
Solution Approach 1:
The patent merges the weak cell information storage function with the existing non-volatile memory structure by utilizing the memory cell array itself as the storage medium. The weak cell information is stored in specific memory cells (e.g., at predetermined addresses) within the array, eliminating the need for a separate dedicated storage circuit and thus reducing chip area while maintaining reliability
Solution Approach 2:
The memory cell array is designed to serve multiple functions: it stores both normal data and weak cell information. By using the same hardware structure for dual purposes, the patent avoids area overhead from dedicated storage circuits while ensuring reliable weak cell detection through the universal memory structure
2Reliability
If memory cells are tested for data retention time, then weak cells are detected, but testing time increases
Solution Approach 1:
The patent performs weak cell detection during the manufacturing process before the memory device is shipped. By conducting the data retention time test preliminarily during fabrication, weak cells are identified and their information is stored in the non-volatile memory before normal operation begins. This eliminates the need for time-consuming weak cell detection during the product's operational lifetime
Solution Approach 2:
The memory device performs self-diagnosis during normal operation by automatically reading weak cell information from storage and comparing it with current cell states. This self-service mechanism allows continuous weak cell monitoring without external testing equipment, significantly reducing testing time while maintaining high detection accuracy
3Reliability
If refresh operations are performed frequently, then data retention is improved, but energy consumption increases
Solution Approach 1:
The patent stores weak cell information (including optimal refresh intervals) in advance during manufacturing. During normal operation, the memory controller reads this pre-stored information and performs refresh operations only for weak cells at their specific intervals, rather than performing uniform frequent refreshes on all cells. This preliminary preparation enables targeted, energy-efficient refresh operations that maintain data retention while minimizing energy consumption
Solution Approach 2:
The patent applies different refresh strategies to different memory cells based on their individual characteristics. Weak cells identified during manufacturing receive customized refresh operations at their specific intervals, while normal cells follow standard refresh patterns. This localized approach ensures data retention for vulnerable cells without unnecessarily increasing energy consumption across the entire memory array
Data Source
AI summary
A semiconductor memory device includes: a weak cell controller for programming weak cell information, outputting the weak cell information in response to an initialization signal or a write end signal, and outputting a read end signal whenever the weak cell information is outputted; a memory cell array region that includes memory cells for storing data in response to a row active signal and a column selection signal, and includes a first cell region for storing the weak cell information; an information transfer control circuit for generating a column address based on a column counting signal generated by using the read end signal, and generating a row address whenever the column counting signal reaches a predetermined value in response to the initialization signal; a row circuit for enabling the row active signal; and a column circuit for outputting the column selection signal by decoding the column address.