Memory Block Wear Leveling Using Dynamic Data Activeness

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Solution Overview

Problem

Existing non-volatile memory devices face inefficiencies in wear leveling due to the use of static data labeling, leading to uneven distribution of write operations and reduced device lifespan due to bit errors.

Innovation Solution

Implementing a method to dynamically label data stored in memory blocks by assigning attributes based on the latest global latest write version number and history write version gap, and moving data between memory blocks to balance wear levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If static data labeling is used for wear leveling, then the implementation is simple, but the wear distribution becomes uneven and device lifespan is reduced

Engineering Contradiction:
Improveimplementation simplicityVSAvoidwear leveling performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies dynamics by transitioning from static data labeling to dynamic attribute assignment. The controller continuously updates data unit attributes based on current wear levels and access patterns, allowing the system to adapt to changing conditions. This enables more effective wear leveling as the labeling reflects real-time device state rather than fixed initial assignments.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes parameters by introducing dynamic attributes that track wear counts and access frequencies. These parameters are continuously updated and used to make intelligent decisions about data placement. The system monitors wear levels across different memory blocks and adjusts data unit assignments based on these parameter changes, achieving better wear distribution.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If dynamic attribute assignment is implemented, then wear leveling performance improves, but the system complexity increases

Engineering Contradiction:
Improvewear leveling performanceVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the memory system into data units with individual attributes. Each data unit is tracked separately with its own wear count and access frequency metrics. This segmentation allows the controller to manage wear leveling at a granular level while maintaining overall system organization through structured attribute management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements feedback mechanisms where the controller continuously monitors wear levels and access patterns, then uses this information to make informed decisions about data placement. The dynamic attributes provide feedback about the current state of each data unit, enabling the system to adjust assignments to optimize wear leveling while managing complexity through rule-based decision making.

Inventive Principle:
Principle #23Feedback

3Duration of action of stationary object

If data is moved between memory blocks based on wear levels, then device lifespan is extended, but the operation time increases

Engineering Contradiction:
Improvedevice lifespanVSAvoidoperation time
Core Design Contradiction:
Duration of action of stationary objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by proactively moving data before wear critical thresholds are reached. The system continuously monitors wear levels and performs data relocation operations in advance, preventing excessive wear accumulation. This proactive approach extends device lifespan by distributing wear more evenly, while the structured attribute system helps manage the time required for these operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12517670B2Methods for controlling memory blocks in memory devices
Publication Date: 2026.01.06 YANGTZE MEMORY TECH CO LTD
  • US12517670B2 patent drawing
  • US12517670B2 patent drawing
  • US12517670B2 patent drawing

AI summary

The present disclosure describes a method of controlling memory blocks. The method comprises determining a first write version number of a first group of address units (AUs) of a plurality of AUs, wherein each AU of the first group of AUs comprises at least one logical block address (LBA) of a plurality of memory blocks and determining a second write version number of the first group of AUs. The method comprises calculating a difference between the first and second write version numbers and determining a third write version number of a second group of AUs of the plurality of AUs. The method further comprises determining a dynamic attribute of the first group of AUs using the first write version number, the difference, and the third write version number, determining an activeness status of the first group of AUs using the dynamic attribute, and moving data based on the activeness status.