Memory Wear Leveling via Block and Line Remapping
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Solution Overview
Problem
Existing wear leveling techniques in memory devices require large look-up tables for fine-grained updates, leading to a reduction in normal memory capacity, as they need to maintain a mapping between logical and physical memory areas to ensure even wear across all memory cells, which is impractical for technologies like flash memory with limited update cycles.
Innovation Solution
Implementing a wear leveling process that uses block and line remapping functions, where logical addresses are translated into physical addresses using a combination of block and line remap tables, allowing for bijective functions like XOR, addition, or bit-swizzling to distribute write operations evenly across memory cells, thereby reducing wear on specific areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a look-up table is maintained to map logical blocks to physical blocks for wear leveling, then wear distribution is improved, but memory capacity is reduced due to the large table size required for fine-grained updates
Solution Approach 1:
The patent segments the wear leveling function into two independent tables: a block remapping table that maps logical blocks to physical blocks, and a line remapping table that maps logical lines to physical lines within blocks. This segmentation allows each table to be smaller and more manageable, reducing the overall memory overhead while maintaining effective wear leveling across the entire memory structure.
Solution Approach 2:
The patent introduces a line-level remapping dimension within each block, transitioning from a simple block-to-block mapping to a two-dimensional mapping approach (block remapping + line remapping). This additional dimension of control enables fine-grained wear leveling at the line level without requiring a single enormous lookup table, thus preserving memory capacity while improving wear distribution.
2Measurement precision
If fine-grained updates are supported with individual update unit mapping, then wear leveling precision is improved, but the translation table size becomes very large, reducing normal memory capacity
Solution Approach 1:
The patent divides the fine-grained mapping function into two separate tables: the block remapping table handles block-level mapping, and the line remapping table handles line-level mapping within blocks. This segmentation achieves fine-grained precision without requiring a single large table, as each table operates at a different granularity level and can be sized appropriately for its specific function.
Solution Approach 2:
The patent applies partial remapping at the line level within blocks rather than requiring complete remapping of all lines. By using the line remapping table to adjust only the necessary line offsets within each block, the system achieves sufficient wear leveling precision without the excessive memory overhead of a complete fine-grained translation table for every possible update unit.
Data Source
AI summary
A method and a corresponding apparatus provide for remapping for wear leveling of a memory. The method is implemented as logic and includes the steps of receiving a memory operation, the memory operation including a logical memory address; dividing the logical address into a logical block address portion, a logical line address portion, and a logical subline address portion; translating the logical block address portion into a physical block address; selecting a line remap key; applying the line remap key to the logical line address portion to produce a physical line address; producing a physical subline address portion; and combining the physical block, line, and subline address portions to produce a physical address for the memory operation.