Memory Wear-Leveling Circuit for Uneven Write Distribution
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Solution Overview
Problem
Existing memory circuits face premature failure due to irregular non-uniform write operations, leading to uneven wear on storage transistors, which current wear-leveling schemes fail to address comprehensively.
Innovation Solution
A control circuit manages read and write operations, implementing a wear-leveling scheme that re-maps memory page addresses algorithmically to distribute write operations evenly across physical memory pages, using a hashing function and triggering events to initiate migration processes, and incorporates a finite state machine for managing migrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If wear-leveling schemes are implemented to distribute write operations, then storage transistor lifespan is extended, but device complexity increases due to additional control circuitry and management overhead
Solution Approach 1:
The memory device performs wear-leveling autonomously through self-managed address remapping. The control circuit automatically monitors write operation counts and redistributes write requests to different physical pages without external intervention, enabling the system to service itself and extend transistor lifespan while managing complexity internally
Solution Approach 2:
The system dynamically changes the mapping parameters between logical and physical page addresses based on write operation history. By adjusting the address translation table and remapping pages with higher write counts to less-used physical pages, the system adapts its parameters to achieve uniform wear distribution across storage transistors
2Reliability
If address remapping is performed frequently to achieve uniform wear distribution, then write operation uniformity is improved, but read latency increases due to migration overhead
Solution Approach 1:
The wear-leveling mechanism operates periodically by triggering address remapping only after a predetermined number of write operations have been performed. This periodic execution ensures uniform wear distribution is achieved at appropriate intervals while avoiding continuous remapping that would cause excessive read latency and performance degradation
Solution Approach 2:
The system performs preliminary wear-leveling remapping before critical write operations accumulate on specific pages. By proactively redistributing write requests to balance wear before it becomes severe, the system prevents the need for more aggressive and latency-intensive corrective remapping operations later
3Reliability
If a comprehensive wear-leveling management scheme is implemented, then premature failure is prevented, but processing time for wear-leveling operations increases
Solution Approach 1:
The control circuit implements partial wear-leveling by focusing remapping operations only on specific page groups that show signs of uneven wear or high write counts, rather than performing comprehensive remapping of all pages. This selective approach achieves sufficient reliability improvement while minimizing the processing time and overhead associated with full-system wear-leveling
Data Source
AI summary
A memory device includes: (a) one or more memory circuits having physical memory pages identified by physical page addresses, each physical memory page being provided to store a memory page; and (b) a control circuit configured for managing read or write operations in each memory circuit. The control circuit manages both a wear-leveling scheme and read and write operations in the memory circuits.