Memory Wear Leveling via Read State Detection
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Solution Overview
Problem
Memory blocks in semiconductor devices experience increased wear due to cycling operations, particularly when in the second read state, leading to reduced lifespan and inaccurate wear level calculation due to varying threshold voltages and environmental factors.
Innovation Solution
A controller is implemented to determine the read state of memory blocks and adjust cycle counts accordingly, incrementing by different values based on whether the block is in a first or second read state to mitigate wear, thereby extending the lifespan and accurately accounting for wear levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cycling operations are performed on memory blocks in the second read state, then read operations can be executed, but wear on the memory block increases over time
Solution Approach 1:
The controller performs a preliminary action by forcing the memory block from the second read state to the first read state before executing the cycling operation. This is achieved by applying a reset voltage to the word line, which discharges the parasitic capacitance and eliminates the coupled-up condition. By performing this preliminary state transition, the controller prevents the harmful effect of increased wear that would occur if cycling were performed directly in the second read state.
2Device complexity
If elapsed time tracking is used to determine read state, then a simple method is provided, but the measurement is inaccurate due to environmental factors and process variations
Solution Approach 1:
The controller implements a feedback mechanism by monitoring the actual state of the memory block (through read operations and status detection) and adjusting its wear calculation accordingly. Rather than relying solely on predetermined time intervals, the controller continuously checks whether the memory block is in the first or second read state and uses this real-time information to determine the appropriate wear increment, thereby achieving accurate measurement despite environmental variations.
Solution Approach 2:
The patent replaces the mechanical/time-based wear tracking system with an electrical state-detection system. Instead of using elapsed time as a proxy for wear state, the controller directly detects the electrical state of the memory block (first read state vs. second read state) through voltage measurements and read operation responses. This substitution of direct electrical sensing for time-based estimation eliminates the inaccuracies caused by environmental factors and process variations.
3Device complexity
If wear level is calculated without accounting for second read state, then calculation is simpler, but wear level accuracy is reduced
Solution Approach 1:
The controller applies local quality by differentiating the wear calculation based on the local state of the memory block. When the memory block is in the second read state, the controller applies a different wear increment (higher value) compared to when it is in the first read state. This localized adjustment to the wear calculation, based on the specific operational state, ensures that the cumulative wear level accurately reflects the actual stress experienced by different portions of the memory block's operational history.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively manages wear levels across memory blocks by accounting for cycling events in the second read state, extending the lifespan of memory blocks and providing accurate wear level calculations, reducing premature failure and ensuring even wear distribution.
Implementation Method 1
The controller is configured to determine whether the memory block is in the first read state or the second read state... The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block
Implementation Method 2
After a first read operation, parasitic capacitances are built up, which place the WLs in the second read condition
Data Source
AI summary
A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.