Nonvolatile Memory Wear-Leveling via Dynamic Write Order

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Solution Overview

Problem

In nonvolatile memory devices, large block sizes lead to uneven usage of word lines due to merge operations, resulting in significant endurance differences between word lines within the same memory block, affecting memory endurance.

Innovation Solution

A method is introduced to control write operations by determining the write order of data in memory blocks based on write indication information, alternating between ascending and descending orders to evenly access memory regions or word lines, using a memory controller with an address conversion controller and address generator to convert logical addresses into physical addresses accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If block size is increased to provide high capacity, then storage capacity is improved, but endurance uniformity deteriorates due to uneven word line usage

Engineering Contradiction:
Improvestorage capacityVSAvoidendurance uniformity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements dynamic write order selection that adapts based on the number of valid data pages. When valid pages are concentrated at the beginning, writes proceed in ascending order; when concentrated at the end, writes proceed in descending order. This dynamic adaptation ensures uniform wear distribution across all word lines while maintaining large block sizes for high capacity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the write operation parameter (write direction/order) based on the distribution of valid data pages. By monitoring the valid page distribution and switching between ascending and descending write orders, the system optimizes wear leveling without requiring smaller block sizes, thus maintaining high storage capacity while improving endurance uniformity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If merge operation is performed early in large blocks, then write speed is improved, but wear leveling deteriorates due to non-uniform word line access

Engineering Contradiction:
Improvewrite speedVSAvoidwear leveling
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically selects write order based on valid page distribution. When valid pages are at the beginning of the block, ascending write order is used; when at the end, descending write order is used. This allows early merge operations to proceed efficiently while ensuring uniform wear distribution across word lines, resolving the contradiction between write speed and wear leveling.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If word lines are accessed sequentially from the beginning, then address generation is simplified, but wear uniformity deteriorates with large block sizes

Engineering Contradiction:
Improveaddress generation complexityVSAvoidwear uniformity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic address generation that switches between ascending and descending orders based on valid page distribution. This maintains relatively simple address generation logic while achieving uniform wear distribution, as the switch between two simple patterns is less complex than implementing sophisticated wear-leveling algorithms.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Instead of always accessing word lines from the beginning in ascending order, the patent inverts the access pattern by using descending order when valid pages are concentrated at the end of the block. This inversion approach maintains simplicity while achieving uniform wear distribution across all word lines.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS9372790B2Nonvolatile memory device having wear-leveling control and method of operating the same
Publication Date: 2016.06.21 SAMSUNG ELECTRONICS CO LTD
  • US9372790B2 patent drawing
  • US9372790B2 patent drawing
  • US9372790B2 patent drawing

AI summary

A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes multiple memory blocks. The method includes reading write indication information with respect to at least a selected memory block of the multiple memory blocks; determining whether a write order of data to be stored in the selected memory block is an ascending order or a descending order, based on the write indication information of the selected memory block; and generating addresses of memory regions in the selected memory block in an ascending order when the write order of the data is determined to be an ascending order, and generating addresses of the memory regions in the selected memory block in a descending order when the write order is determined to be a descending order.