In-Memory Weight Mapping Using Split Cells and Timed Activation
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Solution Overview
Problem
Existing in-memory computation (IMC) devices face inefficiencies in mapping computation weights with a high number of bits, as manufacturing memory cells with a high number of resistance levels is technologically challenging, and existing methods do not effectively utilize two memory cells to achieve the desired bit accuracy.
Innovation Solution
The IMC device organizes memory cells into groups, with each group comprising a most significant cell and a least significant cell, where the resistance levels of these cells are programmed to represent different bits of the computation weight, and activation signals with varying durations are used to perform MAC operations, allowing efficient mapping of computation weights with a higher number of bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each computation weight is mapped in a single memory cell with high number of bits, then processing accuracy is improved, but manufacturing complexity increases significantly
Solution Approach 1:
The patent divides a high-bit computation weight into multiple lower-bit memory cells. Each memory cell stores a portion of the computation weight (e.g., 4 bits per cell), and multiple cells work together to represent the complete high-precision weight. This segmentation allows the system to achieve high processing accuracy without requiring individual memory cells to have high bit capacity, thus avoiding manufacturing complexity.
2Quantity of substance
If each computation weight is mapped in two memory cells with simultaneous activation, then weight-mapping density is improved, but processing accuracy is limited
Solution Approach 1:
The patent introduces dynamic activation windows where memory cells are activated at different time intervals rather than simultaneously. The activation duration and timing of each cell are dynamically controlled to enable sequential contribution to the MAC operation. This dynamic approach allows multiple cells to be effectively combined, achieving both high weight-mapping density and high processing accuracy through temporal multiplexing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the IMC device to efficiently map computation weights with a higher number of bits, improving processing accuracy and weight-mapping density while maintaining low computation times and reducing power consumption.
Implementation Method 1
The resistive element 4 may be programmed in such a way as to have one of 2N resistance levels as a function of a computation weight
Implementation Method 2
Each memory cell 3 l,j comprises a resistive element 4 and a selection element 5, arranged in series with each other
Implementation Method 3
comprise a read circuit having a respective analog-to-digital converter (ADC) which discretizes said current
Data Source
Figure 1
Figure 2
Figure 3~6
AI summary
An in-memory computation device has: an array (12) with a group of cells (22i,j) having a first cell (MSC) with a first number of bits, couplable to a first bit line and programmable to have a first electrical quantity as a function of a first weight (Gij) and a second cell (LSC) with a second number of bits, couplable to a second bit line and programmable to have a second electrical quantity as a function of the first weight; and an activation circuit (14) that provides a first activation signal (Sj,MSC) to the first cell during a first window (CW1) and a second activation signal (Sj,LSC) to the second cell during a second window distinct from the first window, where the activation signals have respective durations that are function of an input value (xj) and, optionally, also of at least one of the first and second number of bits. The device also has a read circuit that generates a first signal (Qi,MSC) indicative of a time integral of the current of the first bit line during the first window, generates a second signal (Qi,LSC) indicative of a time integral of the current of the second bit line during the second window, and that provides a digital signal (qi) indicative of a sum between the first and the second signals, optionally also as a function of at least one of first and second number of bits.