In-Memory Weight Mapping Using Split-Cell Time Integration
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Solution Overview
Problem
Existing in-memory computation (IMC) devices face inefficiencies in mapping computation weights with a high number of bits, as manufacturing memory cells with a high number of bits is technologically challenging, and existing methods do not efficiently utilize memory cells to achieve the desired accuracy.
Innovation Solution
The IMC device employs a memory array with groups of memory cells, including a most significant cell and a least significant cell, where each cell is activated during distinct computation windows with durations determined by the input value and the number of bits, allowing for the integration of currents over these windows to generate a digital signal representing the computation weight, effectively doubling the number of bits mapped.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each computation weight is mapped in a single memory cell with a high number of bits, then the processing accuracy is improved, but the manufacturing complexity increases significantly
Solution Approach 1:
The computation weight mapping is segmented across multiple memory cells (first memory cell with first number of bits, second memory cell with second number of bits) instead of requiring a single high-bit memory cell. This segmentation allows the system to achieve high processing accuracy through combined information from multiple cells while maintaining compatibility with standard manufacturing processes for lower-bit memory cells.
2Measurement precision
If two memory cells are used to map each computation weight, then the effective number of bits is increased, but the computation time increases due to simultaneous activation
Solution Approach 1:
The first and second memory cells are activated in distinct, non-overlapping computation windows rather than simultaneously. The first memory cell is activated during a first computation window, and the second memory cell is activated during a second computation window. This periodic activation approach maintains the effective bit increase benefit while reducing the overall computation time by eliminating simultaneous operation overhead.
3Quantity of substance
If memory cells with different numbers of bits are used, then the weight-mapping density is improved, but the device complexity increases
Solution Approach 1:
Different memory cells are assigned different numbers of bits (first memory cell with first number of bits, second memory cell with second number of bits) based on their specific role in representing the computation weight. This local quality differentiation optimizes the weight-mapping density by allocating bit resources according to actual needs, while the overall device complexity is managed through a standardized memory cell architecture that can accommodate varying bit configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of mapping computation weights with a high number of bits, improving the weight-mapping density and reducing computation time while maintaining low activation times.
Implementation Method 1
Each memory cell 31,j comprises a resistive element 4 and a selection element 5, arranged in series with each other. The resistive element 4 may be programmed in such a way as to have one of 2N resistance levels
Implementation Method 2
the first memory cell is configured to be traversed, during the first computation window, by a first cell current which is a function of the first electrical quantity and the first activation duration
Data Source
AI summary
A group of memory cells includes a first cell with a first number of bits, coupled to a first bit line and programmable with a first weight and a second cell with a second number of bits, coupled to a second bit line and programmable with the first weight. An activation circuit applies first and second activation signals to the first and second cells during first and second windows, respectively. The activation signals have respective durations as a function of an input value and, optionally, a number of bits of the first or second cell. A read circuit generates first and second signals indicative of a time integral of current in the first and second bit lines during the first and second windows, respectively, and outputs a digital signal indicative of a sum between the first and second signals, optionally also as a function of number of bits.