Semiconductor Memory Well Biasing for Noise Margin
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Solution Overview
Problem
Conventional memory devices face issues with weak cells having low static noise margin and write margin, which worsen as voltage decreases, leading to cell failures and increased power consumption due to the need to bias entire arrays or blocks simultaneously.
Innovation Solution
The solution involves biasing n-wells and p-wells on a local level, allowing for fine-tuned biasing and reducing overhead, using a block select unit to supply biasing voltages to groups of cells, and employing triple well technology to enable efficient back biasing, reducing capacitance and improving noise margins and write performance at lower voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate biasing of individual transistor substrates is implemented, then static noise margin and write margin are improved, but device size increases significantly
Solution Approach 1:
The memory device is divided into multiple blocks, with each block containing a subset of memory cells that share common n-well and p-well structures. This segmentation allows independent biasing of each block while maintaining shared wells within blocks, reducing the overall number of biasing circuits needed compared to individual transistor biasing.
Solution Approach 2:
Each block is equipped with its own biasing circuit that can independently control the substrate bias voltage for that specific block. This local biasing approach allows fine-tuned control of noise margins where needed while avoiding the area overhead of biasing every individual transistor throughout the entire memory device.
2Reliability
If separate biasing of individual transistor substrates is implemented, then write margin is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple blocks, with each block containing a subset of memory cells that share common n-well and p-well structures. This segmentation allows independent biasing of each block while maintaining shared wells within blocks, reducing the overall number of biasing circuits needed compared to individual transistor biasing.
Solution Approach 2:
Each block is equipped with its own biasing circuit that can independently control the substrate bias voltage for that specific block. This local biasing approach allows fine-tuned control of noise margins where needed while avoiding the area overhead of biasing every individual transistor throughout the entire memory device.
3Reliability
If biasing is applied to entire arrays or blocks simultaneously, then noise margins are improved, but power consumption increases
Solution Approach 1:
The biasing system is designed to dynamically activate only the blocks that are currently being accessed or operated on. When a specific block is selected for read or write operations, its biasing circuit is activated to provide the necessary substrate bias voltage. Blocks that are not currently in use maintain their bias circuits in a low-power state, significantly reducing overall power consumption compared to keeping all blocks biased simultaneously.
4Area of stationary object
If conventional biasing structures are used, then device area is minimized, but static noise margin approaches zero
Solution Approach 1:
The invention changes the electrical parameters of the wells by applying adjustable substrate bias voltages to the n-wells and p-wells. By dynamically controlling the bias voltage level, the noise margin can be optimized without requiring larger cell dimensions. This parameter adjustment allows maintaining compact cell area while achieving adequate noise margins through electrical tuning rather than physical scaling.
Data Source
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AI summary
A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve readingand writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.