Memory Macro Well Isolation Using Cut Metal Gate Trenches
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Solution Overview
Problem
As semiconductor devices scale down, leakage current between oppositely doped wells increases, leading to latch-up issues in memory devices due to dopant diffusion, which existing technologies fail to adequately address in advanced process nodes.
Innovation Solution
The implementation of well isolation features through a cut metal gate process, where CMG trenches are etched along every well boundary in well pick-up and middle strap areas, filled with an isolation material to separate adjacent oppositely doped wells, effectively reducing leakage and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased through scaling down, then production efficiency is improved and costs are lowered, but leakage between adjacent n-type wells and p-type wells becomes more severe due to dopant diffusion
Solution Approach 1:
The patent introduces well isolation features (trenches filled with dielectric material) that segment and physically separate adjacent n-type wells and p-type wells. This segmentation prevents dopant diffusion between wells, thereby reducing leakage current while maintaining the scaled-down geometry for high production efficiency
Solution Approach 2:
The patent employs dielectric material as an intermediary substance filling the well isolation trenches. This intermediary layer acts as a barrier between oppositely doped wells, blocking dopant diffusion paths and reducing leakage current without interfering with the electrical operation of the memory devices
2Quantity of substance
If geometry size is decreased through scaling down, then functional density is increased, but latch-up issues worsen due to increased well resistance from dopant diffusion
Solution Approach 1:
By segmenting the well structures with isolation trenches, the patent prevents lateral dopant diffusion that would otherwise increase well resistance. This maintains low well resistance even at scaled dimensions, reducing latch-up susceptibility while preserving high functional density
Solution Approach 2:
The patent extracts or removes the harmful dopant diffusion paths by introducing isolation trenches. This extraction of the diffusion pathway prevents the accumulation of unwanted dopants at well boundaries, thereby maintaining electrical integrity and reducing latch-up risk in high-density configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leakage between oppositely doped wells, lowers well pick-up resistance, and minimizes the likelihood of latch-up, with observed reductions up to 8 times compared to designs without well isolation structures.
Implementation Method 1
leakage between adjacent n-type wells (or N wells) and p-type wells (or P wells) becomes more severe in advanced process nodes due to dopant diffusion
Data Source
AI summary
A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.