3D Memory Wiring Layout for Narrower Connection Regions
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in efficiently connecting conductive layers and reducing the width of connection regions, leading to increased complexity and area usage due to the need for multiple wirings in the Y-direction.
Innovation Solution
The semiconductor memory device employs a configuration with a substantially staircase pattern in the hook-up regions, where conductive layers are separated and connected using contacts and through contacts, reducing the number of wirings required in the Y-direction and minimizing the connection region width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple wirings are used in the Y-direction to connect conductive layers, then connectivity between conductive layers is improved, but the width of the connection region increases
Solution Approach 1:
The patent transitions from planar wiring connections to three-dimensional vertical connections through contacts and through contacts. Conductive layers are connected by extending connections in the vertical direction (Z-direction) rather than solely in the horizontal Y-direction, thereby reducing the connection region width while maintaining connectivity.
Solution Approach 2:
The patent divides the connection structure into multiple discrete elements: contacts for connecting lower conductive layers, through contacts for connecting upper conductive layers, and separate connection regions. This segmentation allows independent optimization of each connection path, reducing the overall connection region width while ensuring reliable connectivity.
2Area of stationary object
If the connection region width is reduced, then space efficiency is improved, but the complexity of connecting conductive layers increases
Solution Approach 1:
The patent combines multiple connection functions into integrated structures. Through contacts serve dual purposes by connecting both upper and lower conductive layers simultaneously. Connection regions are merged and overlapped between adjacent memory blocks, reducing the total connection region width while distributing the connection complexity across shared structures.
Solution Approach 2:
The contact structures are designed with multi-functionality: contacts serve as connection points for multiple conductive layers, through contacts provide both local and long-range connections, and the same connection region structure is universally applied across adjacent memory blocks. This universality reduces overall complexity by using standardized multi-functional elements.
Data Source
AI summary
A semiconductor memory device includes a substrate including a first to a fourth region, first conductive layers from the first to second region, second conductive layers from the fourth to second region, third conductive layers from the first to third region, fourth conductive layers from the fourth to third region, a first semiconductor column opposed to the first and third conductive layers in the first region, a second semiconductor column opposed to the second and fourth conductive layers in the fourth region, first and second contacts connected to the first and the second conductive layers in the second region, third and fourth contacts connected to the third and fourth conductive layers in the third region, first wirings connected to the first and second contacts in the second region, and second wirings connected to the third and fourth contacts in the third region.