3D Memory Cell Wiring Layout for Reliable Layer Integration
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Solution Overview
Problem
Current semiconductor storage devices face challenges in efficiently integrating and connecting various layers and components, such as conductive layers, semiconductor layers, and charge storage layers, which affects the overall performance and reliability of the memory cell array.
Innovation Solution
The semiconductor storage device incorporates a substrate with a first wiring layer, a second wiring layer, a memory cell array layer, and a first insulating layer, where the memory cell array layer includes conductive layers, a semiconductor layer, and a charge storage layer, with specific electrical connections and coverage configurations to enhance integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple conductive layers and semiconductor layers are integrated in a stacked configuration, then the storage capacity and integration density are improved, but the manufacturing complexity and connection reliability deteriorate
Solution Approach 1:
The device is divided into distinct functional layers including charge storage layers, tunnel insulating layers, block insulating layers, and semiconductor layers. Each layer is independently formed with specific materials and structures, allowing complex functionality to be achieved through modular stacking while simplifying the manufacturing process for each individual layer.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacked integration by arranging multiple functional layers vertically. This vertical stacking in the thickness direction enables higher integration density without increasing the planar footprint, effectively adding a dimensional aspect to the device architecture.
2Quantity of substance
If multiple conductive layers and semiconductor layers are integrated in a stacked configuration, then the storage capacity and integration density are improved, but the connection reliability deteriorates
Solution Approach 1:
Different regions of the device employ different structural configurations optimized for their specific functions. For example, charge storage layers have specific thickness ranges (5-50 nm) and material compositions tailored for charge retention, while tunnel insulating layers use specific materials (oxide, nitride, or their combinations) with controlled thicknesses to ensure reliable charge injection and blocking functions.
Solution Approach 2:
The patent utilizes composite material structures including stacked insulating layers (oxide+nitride), combined barrier layers, and multi-material conductive layers. These composite structures provide enhanced interface quality, improved charge retention characteristics, and better overall connection reliability between the stacked functional layers.
3Productivity
If the memory cell array layer is positioned between the substrate and the second wiring layer with specific coverage, then the electrical connection efficiency is improved, but the device structure complexity increases
Solution Approach 1:
The first wiring layer serves multiple functions: it provides electrical connections to the memory cell array, acts as a structural support layer, and enables subsequent layer formation. The second wiring layer similarly provides both electrical connectivity and structural functionality, allowing the device to achieve high connection efficiency while maintaining manageable structural complexity through multi-functional design.
Solution Approach 2:
The first wiring layer is formed in advance before the second wiring layer and memory cell array layer are stacked. This preliminary formation establishes the electrical connection framework early in the manufacturing process, enabling subsequent layers to be aligned and connected more efficiently while reducing overall device structure complexity.
Data Source
AI summary
A semiconductor storage device includes a substrate, a first wiring layer, a second wiring layer, a memory cell array layer, and a first insulating layer. The memory cell array layer includes a plurality of first conductive layers that are arranged in a first direction, a first semiconductor layer that faces the plurality of first conductive layers, a first charge storage layer that is provided between the plurality of first conductive layers and the first semiconductor layer, and first and second contacts that extend in the first direction. The second wiring layer includes a second conductive layer that is connected to one end of the first semiconductor layer. The first wiring layer includes first and second electrodes that are connected to the first and second contacts. At least a part of surfaces of the first and second electrodes on a substrate side is closer to the substrate than a surface of the second conductive layer on the side opposite to the substrate in the first direction. A surface of the first electrode on the side opposite to the substrate includes a region that is not covered with the first insulating layer. A surface of the second electrode on the side opposite to the substrate is entirely covered with the first insulating layer.