Nonvolatile Memory Lead-out Wiring via Merged Wire Layers
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices face challenges in forming high-density lead-out contacts with low process costs due to the difficulty in electrically connecting conductive and semiconductor layers, leading to increased masks and process steps, which hinders high-dense integration and cost-effectiveness.
Innovation Solution
A cross-point nonvolatile semiconductor memory device configuration that includes a substrate with stripe-shaped memory wires, interlayer insulating layers, and resistance variable layers, where non-ohmic elements are integrated into the wire layer, allowing for direct contact formation without additional intervening layers, enabling efficient connection and reduced parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lead-out wires are connected to peripheral circuits using conventional wiring structures, then electrical connection is achieved, but high-dense integration is impeded due to increased process complexity and chip area
Solution Approach 1:
The patent merges the lead-out wire structure with the peripheral circuit wiring by forming both structures simultaneously using the same wire formation process. The wire layer is extended to serve dual purposes: as memory cell interconnects and as peripheral circuit leads, eliminating the need for separate lead-out wire structures and reducing overall device complexity
Solution Approach 2:
The wire layer is designed to perform multiple functions: it serves as both the interconnect for memory cells and as the lead-out connection for peripheral circuits. This multi-functional design allows a single wire structure to fulfill multiple electrical connection requirements, reducing the number of additional masks and process steps needed
2Reliability
If additional masks and process steps are used to form lead-out contacts, then electrical connection to underlying wire layers is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent combines the formation of lead-out contacts with the formation of memory cell contacts into a single contact formation process. Contacts are formed at specific locations where the wire layer is discontinuous, allowing simultaneous access to underlying wire layers for both memory cells and peripheral circuits without requiring separate processing steps
Solution Approach 2:
The patent extracts the lead-out function from the wire layer by creating localized discontinuities or openings in the wire structure. This allows direct access to underlying wire layers at specific points, enabling lead-out connections to be formed using the same contact process used for memory cells, without adding extra manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures sufficient current supply, high-density integration, and reduced process complexity and cost, allowing for high-speed memory operations while maintaining reliability.
Implementation Method 1
a nonvolatile semiconductor memory device (hereinafter referred to as ReRAM) using a material which is adapted to change a resistance value in response to electric pulses applied and retains the changed resistance value
Implementation Method 2
a nonvolatile semiconductor memory device (hereinafter referred to as MRAM) which retains a changed resistance value by utilizing a tunneling magnetic resistive effect
Data Source
AI summary
A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).