Memory Wiring Layout Using RC Effects for Higher Density
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing data storage capacity and reducing chip size while maintaining efficient area utilization.
Innovation Solution
Incorporating a wiring structure that acts as an RC element, with adjacent and crossing lines, to enhance area efficiency by generating additional RC through an out-of-circuit layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent merges the RC element functionality into the wiring structure itself by positioning conductive lines adjacent to each other with insulating layers interposed, creating parasitic RC effects that are utilized for delay generation. This eliminates the need for separate RC element circuits, thereby increasing storage capacity while managing device complexity.
Solution Approach 2:
The wiring structure serves dual purposes: it provides electrical connectivity for memory cell operations and simultaneously functions as an RC element for signal delay control. This multi-functionality allows the same structure to support both high-capacity storage and timing control without adding separate dedicated components.
2Area of stationary object
If wiring structure with adjacent and crossing lines is used to generate additional RC, then area efficiency is improved, but device complexity increases
Solution Approach 1:
The patent utilizes three-dimensional wiring arrangement with lines extended in different directions (first direction and second direction) and spaced apart with insulating layers. This spatial arrangement in multiple dimensions creates additional RC effects without consuming extra planar area, improving area efficiency while the structured dimensional approach manages complexity.
Solution Approach 2:
The wiring structure employs nested arrangement where conductive lines are positioned in different layers with insulating layers interposed between them. This nesting approach allows multiple wiring functions and RC generation within a compact volume, improving area efficiency while maintaining organized structure to manage complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves chip area efficiency and enhances data storage capacity without increasing chip size, thereby optimizing semiconductor memory device performance.
Implementation Method 1
the first wiring structure configured to receive a first voltage at one end thereof, the first wiring structure configured to receive a second voltage different from the first voltage at the other end thereof due to resistance of the first wiring structure
Implementation Method 2
the first wiring structure and the second wiring structure spaced apart from each other with an insulating layer interposed therebetween
Data Source
AI summary
A semiconductor memory device including a memory cell array and a peripheral circuit element configured to control an operation of the memory cell array, and a wiring structure including first and second wiring structures spaced apart from each other on the peripheral circuit element, a first voltage and a second voltage different from the first voltage applied to two opposite ends of the first wiring structure, respectively, and a third voltage different from the first and second voltages applied to the second wiring structure, may be provided. The first wiring structure includes first lines extended in a first direction and spaced apart from each other in a second direction crossing the first direction, the second wiring structure includes second lines extended in the first direction and spaced apart from each other in the second direction, and one of the first lines is between the second lines.