Semiconductor Memory Wiring Layout for Denser Row Control Circuits
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing the integration of transistors and wiring layers, leading to increased circuit area and reduced integration density due to the large area requirements of row control circuit regions, which affects the overall performance and density of memory devices.
Innovation Solution
The semiconductor memory device incorporates a configuration where a part of the row control circuit regions are disposed in regions overlapping with hook-up regions when viewed in the Z-direction, and the remaining parts are placed in memory hole regions, with specific wiring patterns and connecting portions to reduce the circuit area and enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row control circuit regions are disposed separately from hook-up regions, then circuit functionality is ensured, but circuit area increases and integration density decreases
Solution Approach 1:
The patent merges the row control circuit regions with the hook-up regions by disposing them in overlapping positions when viewed in the Z-direction. This integration allows the row control circuits to be formed in the same planar space as the hook-up regions, reducing the overall circuit area while maintaining both functionalities through three-dimensional spatial arrangement.
Solution Approach 2:
The patent utilizes the Z-direction (vertical dimension) to resolve the spatial conflict between row control circuit regions and hook-up regions. By allowing overlap in the Z-direction while maintaining separate functional layers, the design transitions from a two-dimensional layout constraint to a three-dimensional spatial solution, thereby reducing planar area occupation.
2Reliability
If row control circuit regions are disposed separately from hook-up regions, then circuit functionality is ensured, but integration density decreases
Solution Approach 1:
The patent merges the row control circuit regions with the hook-up regions by disposing them in overlapping positions when viewed in the Z-direction. This integration allows the row control circuits to be formed in the same planar space as the hook-up regions, reducing the overall circuit area while maintaining both functionalities through three-dimensional spatial arrangement.
Solution Approach 2:
The patent utilizes the Z-direction (vertical dimension) to resolve the spatial conflict between row control circuit regions and hook-up regions. By allowing overlap in the Z-direction while maintaining separate functional layers, the design transitions from a two-dimensional layout constraint to a three-dimensional spatial solution, thereby reducing planar area occupation.
Data Source
AI summary
A semiconductor memory device includes a plurality of transistors arranged in a first direction, and arranged in a second direction and a first wiring layer disposed between a semiconductor substrate and a plurality of voltage supply wirings. Each of the plurality of transistors includes a source region and a drain region. The first wiring layer includes a plurality of first connecting portions disposed at positions overlapping with the plurality of source regions when viewed in a third direction and electrically connected to the plurality of source regions and the plurality of voltage supply wirings, a plurality of second connecting portions disposed at positions overlapping with the plurality of source regions when viewed in the third direction and electrically connected to a plurality of the drain regions and a plurality of conductive layers, and a passing wiring region disposed between a pair of the second connecting portions.