Semiconductor Memory Wiring Segmentation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently integrating and connecting bit lines and sense amplifiers due to the complex wiring patterns and overlapping regions, leading to increased circuit area and manufacturing difficulties.
Innovation Solution
The semiconductor memory device employs a specific wiring pattern in the wiring layer M1, where wiring groups Gm1 and Gm2 are arranged in a manner that allows bit lines to connect to sense amplifiers without interference from via-contact electrodes, reducing the need for bending and simplifying the manufacturing process by optimizing the pitch and arrangement of wirings m1a and d4.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex wiring patterns are used to connect bit lines and sense amplifiers, then connection reliability is improved, but device complexity and circuit area increase
Solution Approach 1:
The chip is divided into a memory cell array region and a column control circuit region, with wiring groups segmented into first wiring groups connecting bit lines to sense amplifiers and second wiring groups connecting sense amplifiers to latch circuits. This segmentation organizes the complex wiring into manageable segments, reducing overall device complexity while maintaining connection reliability.
Solution Approach 2:
The patent utilizes multiple wiring layers (first wiring layer and second wiring layer) to connect components. By transitioning from a single-plane wiring approach to a multi-layer three-dimensional wiring structure, the patent achieves reliable connections between bit lines and sense amplifiers without increasing planar circuit area or wiring complexity in any single layer.
2Ease of manufacture
If wiring groups are arranged to avoid via-contact electrode interference, then manufacturing ease is improved, but wiring arrangement complexity increases
Solution Approach 1:
The patent performs preliminary routing planning where first wiring groups are arranged to connect bit lines to sense amplifiers without interfering with via-contact electrodes, and second wiring groups are preliminarily arranged to connect sense amplifiers to latch circuits. This preliminary arrangement prevents manufacturing conflicts before the actual manufacturing process, simplifying production while managing wiring complexity through advance planning.
Solution Approach 2:
Different wiring groups are assigned different local functions and arrangements: first wiring groups are locally optimized for bit line to sense amplifier connections avoiding via-contact electrodes, while second wiring groups are locally optimized for sense amplifier to latch circuit connections. This local quality differentiation allows each wiring group to be manufactured with appropriate simplicity while managing overall wiring arrangement complexity.
3Area of stationary object
If circuit area is reduced through optimized wiring, then integration density is improved, but wiring pitch optimization difficulty increases
Solution Approach 1:
The wiring structure is segmented into distinct first wiring groups and second wiring groups with different functions and pitch requirements. This segmentation allows each group to be optimized independently for minimal area occupation, reducing total circuit area while managing pitch optimization difficulty through localized optimization strategies for each wiring segment.
Solution Approach 2:
The patent employs multiple wiring layers to route signals, transitioning from two-dimensional planar wiring to three-dimensional multi-layer wiring. This dimensional change allows wiring groups to be stacked vertically, reducing planar circuit area while distributing pitch optimization challenges across multiple layers, thereby managing optimization difficulty.
Data Source
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AI summary
A semiconductor memory device includes a plurality of sense amplifier regions, a first wiring layer including a plurality of bit lines electrically connected to a plurality of semiconductor layers, and a second wiring layer including a plurality of first wirings electrically connecting the respective plurality of sense amplifier regions to the plurality of bit lines. The semiconductor substrate includes a first region and a second region arranged in a second direction. The (n1) (n1 is an integer of 2 or more) first wirings arranged in the third direction are disposed at a position where the first region overlaps with the sense amplifier region viewed in the first direction. The (n2) (n2 is an integer of 2 or more different from n1) first wirings arranged in the third direction are disposed at a position where the second region overlaps with the other sense amplifier region viewed in the first direction.