Memory Wiring Layout for Dense Sense Amplifier Connections
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in efficiently integrating and connecting the column control circuit region with the row control circuit region and memory blocks due to the complex wiring patterns and interference from via-contact electrodes, leading to increased manufacturing difficulties and reduced integration density.
Innovation Solution
The semiconductor memory device incorporates a wiring layer configuration with alternating regions of different division units, such as R(6div) and R(8div), allowing the wirings m1a to pass through without interference, and utilizing separate wirings m1c to connect via-contact electrodes to word line switches, thereby reducing crowding and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If complex wiring patterns are used to connect column control circuit region with row control circuit region and memory blocks, then connectivity is achieved, but manufacturing complexity increases and integration density decreases
Solution Approach 1:
The chip is divided into distinct regions with different wiring division units (e.g., R(6div) and R(8div)). The column control circuit region is separated from the row control circuit region, with dedicated wiring layers and via-contact electrodes for each region. This segmentation allows simpler wiring patterns within each region while maintaining overall connectivity.
Solution Approach 2:
Multiple wiring layers are employed to connect circuit regions vertically. The first wiring layer connects bit lines to via-contact electrodes, while the second wiring layer connects via-contact electrodes to word line switches. This multi-layer approach reduces the complexity of planar wiring patterns by utilizing the vertical dimension.
2Productivity
If via-contact electrodes are densely arranged to connect wirings, then connectivity is improved, but wiring crowding increases and integration density decreases
Solution Approach 1:
The via-contact electrodes are extracted and positioned in dedicated connection regions between the column control circuit region and row control circuit region. This separation allows wirings to pass through connection regions without interference from via-contact electrodes in other areas, reducing wiring crowding while maintaining integration density.
Solution Approach 2:
Connection regions with via-contact electrodes serve as intermediary zones between the column control circuit region and row control circuit region. These intermediary regions facilitate wiring connections without causing crowding in the main circuit areas, as wirings can extend through connection regions without interference.
3Reliability
If wirings are extended to connect circuit regions, then connectivity is improved, but interference from via-contact electrodes increases manufacturing difficulty
Solution Approach 1:
Different regions of the chip have different wiring division units and via-contact electrode arrangements. Connection regions are specifically designed with via-contact electrodes positioned to allow wiring extension without interference. This local optimization ensures reliable connectivity in critical areas while simplifying manufacturing in other regions.
Data Source
AI summary
A semiconductor memory device includes a plurality of sense amplifier regions, a first wiring layer including a plurality of bit lines electrically connected to a plurality of semiconductor layers, and a second wiring layer including a plurality of first wirings electrically connecting the respective plurality of sense amplifier regions to the plurality of bit lines. The semiconductor substrate includes a first region and a second region arranged in a second direction. The (n1) (n1 is an integer of 2 or more) first wirings arranged in the third direction are disposed at a position where the first region overlaps with the sense amplifier region viewed in the first direction. The (n2) (n2 is an integer of 2 or more different from n1) first wirings arranged in the third direction are disposed at a position where the second region overlaps with the other sense amplifier region viewed in the first direction.