Multi-Layer Wiring Sheet Resistance Reduction in Nonvolatile Memory
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices face challenges in reducing wiring sheet resistance, which affects their performance and efficiency.
Innovation Solution
The proposed solution involves a nonvolatile semiconductor memory device with a cross-point type memory structure, where the first, second, and third wiring layers are made of different materials, and different dry etching gases are used for each layer to control etching rates and prevent increased sheet resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same material is used for multiple wiring layers, then the fabrication process is simplified, but the lower wiring layers are etched during processing of upper layers causing increased sheet resistance
Solution Approach 1:
The patent divides the wiring structure into multiple layers (first, second, and third wiring layers) made of different materials. The first wiring layer uses a material with high etching resistance, the second wiring layer uses a material that is etched at a controlled rate, and the third wiring layer uses a material with appropriate etching characteristics. This segmentation allows each layer to be optimized for its specific function while preventing unwanted etching of lower layers.
Solution Approach 2:
The patent applies different materials to different wiring layers based on their specific requirements. The first wiring layer (lower layer) uses a material with high etching resistance to protect it from being etched during upper layer processing. The second and third wiring layers use materials with controlled etching rates that allow them to be properly formed without affecting lower layers. This local differentiation of material properties resolves the contradiction between fabrication simplicity and sheet resistance maintenance.
2Reliability
If different materials are used for different wiring layers, then etching control is improved preventing sheet resistance increase, but the fabrication process complexity increases
Solution Approach 1:
The patent changes the material parameters (etching resistance, etching rate) for different wiring layers to achieve the desired etching control. By selecting materials with specific etching characteristics, the patent enables selective etching of upper layers without affecting lower layers, thereby maintaining low sheet resistance while managing fabrication complexity through systematic material selection.
Solution Approach 2:
The patent employs a composite multi-layer wiring structure where each layer is composed of different materials optimized for its function. The first wiring layer may use materials like tungsten or cobalt with high etching resistance, while upper layers use materials with controlled etching rates. This composite approach allows precise control of etching processes and maintains electrical performance.
3Productivity
If the etching rate of upper wiring layers is increased for faster fabrication, then productivity is improved, but the lower wiring layers are more likely to be etched causing performance degradation
Solution Approach 1:
The patent prepares the wiring structure in advance by forming lower wiring layers with materials that have high etching resistance before forming upper layers. This preliminary action ensures that when aggressive etching is applied to upper layers for productivity, the lower layers are already protected and will not be etched, thus maintaining device performance while enabling faster fabrication.
Solution Approach 2:
The patent provides a cushioning effect by using materials with high etching resistance in lower wiring layers. This beforehand cushioning protects the lower layers from the harmful effects of aggressive etching applied to upper layers, allowing faster fabrication processes without compromising the integrity or performance of the memory device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the wiring sheet resistance by preventing the lower wiring layers from being etched during the processing of upper layers, thereby enhancing the performance and efficiency of the memory device.
Implementation Method 1
different dry etching gases are used for each layer to control etching rates
Data Source
AI summary
A certain embodiment includes: first wiring layers extended in a first direction arranged in a second direction crossing the first direction; second wiring layers, including two layers having mutually different materials, extended in the second direction arranged in the first direction above the first wiring layers; third wiring layers extended in the first direction arranged in the second direction above the second wiring layers; a first memory cell disposed between one second wiring layer and one first wiring layer between the second and first wiring layers; a second memory cell disposed between one third wiring layer and the one second wiring layer between the third and second wiring layers; a third memory cell disposed between the one second wiring layer and another closest first wiring layer adjacent to the first wiring layer having the first memory cell; and an insulation layer disposed between the first and third memory cells.