Semiconductor Memory Word Line Activation Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently performing test operations on normal and redundancy word lines due to the limitations of existing fuse programming methods, which can lead to incomplete detection and repair of defective memory cells, affecting product yield and operational efficiency.
Innovation Solution
A semiconductor memory device with a test control unit that manages the activation of normal and redundancy word lines based on repair information, ensuring equal activation of all lines except for the repair target word line during test operations, utilizing a fuse unit for storing and detecting repair information to control activation signals and restrict enablement accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If physical type fuses are used for programming repair information, then the fuse programming can be performed using a laser beam to physically cut the fuses, but the programming can only be done in the wafer state and not after packaging
Solution Approach 1:
The patent replaces the physical laser-based cutting method with an electrical field-based programming method. Electrical type fuses are programmed by applying a high voltage pulse that ruptures the fuse element, substituting mechanical/optical energy with electrical energy to achieve fuse programming.
Solution Approach 2:
The patent changes the programming parameter from physical cutting (laser beam) to electrical rupture (high voltage pulse). This parameter change enables programming flexibility across different states (wafer and package states) while maintaining the fuse's function of storing repair information.
2Measurement precision
If test operations are performed on all word lines including redundancy word lines, then complete detection of defective memory cells is achieved, but the test operation complexity and time increase
Solution Approach 1:
The patent performs preliminary testing of normal word lines first to identify defective memory cells before testing redundancy word lines. This preliminary action allows the system to determine whether redundancy word line testing is necessary, avoiding unnecessary testing time while ensuring complete detection when needed.
Solution Approach 2:
The patent implements conditional testing where only the necessary portion of word lines are tested based on detected defects. If no defects are found in normal word lines, redundancy word lines are skipped; if defects are found, then redundancy word lines are tested. This partial action approach balances completeness with time efficiency.
3Reliability
If redundancy memory cells are added to substitute defective memory cells, then product yield is improved, but the device complexity and additional circuits required increase
Solution Approach 1:
The patent designs the fuse unit to serve multiple functions: storing repair information for normal word lines, storing repair information for redundancy word lines, and providing activation control signals. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall device complexity while maintaining reliability.
Solution Approach 2:
The patent merges the fuse programming and control functionality into a single integrated fuse unit that handles both normal and redundancy word lines. By combining these functions into one unit rather than having separate circuits for each, the overall device complexity is reduced while still achieving the reliability benefits of redundancy memory cells.
4Adaptability or versatility
If electrical type fuses are used for programming repair information, then programming can be performed in both package state and wafer state, but the fuse programming requires high voltage to rupture the fuses
Solution Approach 1:
The patent utilizes the parameter change of applying high voltage pulses to rupture electrical type fuses. This parameter change enables flexible programming in both wafer and package states while managing energy consumption through controlled pulse duration and voltage levels.
Data Source
AI summary
A semiconductor memory device includes: a word line driving unit suitable for performing activation operations for a plurality of normal word lines and a plurality of redundancy word lines in response to test addresses; and a test control unit suitable for controlling a number of activations of each of the plural normal and redundancy word lines to be equal based on repair information corresponding to a repair target word line among the plural normal word lines during a test operation.