Semiconductor Memory Device Word Line Boosting
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing the read and write operations, particularly in high-speed modes, due to parasitic capacitance and wiring length issues, which affect the speed and efficiency of data processing.
Innovation Solution
The semiconductor memory device employs a configuration where memory cell transistors in certain NAND strings are inhibited during read operations in high-speed mode, allowing for controlled boosting of word lines and reducing parasitic capacitance influence, while selecting blocks based on wiring length to enhance operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory cell transistors are accessed during read operations, then data completeness is ensured, but parasitic capacitance increases and operation speed decreases
Solution Approach 1:
The patent segments the memory cell transistors into two groups: those connected to selected bit lines (first memory cell transistors) and those connected to unselected bit lines (second memory cell transistors). During read operations, only the first memory cell transistors are accessed while the second are inhibited, thereby reducing parasitic capacitance and improving read speed without compromising data completeness for the intended read operation.
2Speed
If word lines are boosted to high voltage for fast programming, then write speed improves, but parasitic capacitance effects increase causing voltage drops
Solution Approach 1:
The patent applies preliminary action by performing an acceleration operation before the main program operation. This acceleration operation pre-charges the word lines and reduces the impact of parasitic capacitance, ensuring that when the high-voltage program pulse is applied, the voltage remains stable and effective for reliable programming while maintaining fast write speeds.
3Quantity of substance
If blocks with longer wiring lengths are used, then memory capacity increases, but operation speed decreases due to RC delays
Solution Approach 1:
The patent applies local quality by differentiating the treatment of memory blocks based on their wiring length characteristics. Blocks with shorter wiring lengths are designated for high-speed mode operations where all transistors can be efficiently accessed, while blocks with longer wiring lengths use normal mode with selective transistor inhibition. This localized optimization ensures each block operates at its optimal speed regardless of wiring length, maintaining overall system performance while maximizing memory capacity.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor; a second memory string including a second memory cell transistor; a first word line commonly coupled to a gate of each of the first memory cell transistor and the second memory cell transistor; and a control circuit, wherein during a first read operation of reading data from the first memory string, a threshold voltage of the first memory cell transistor is less than a first voltage, a threshold voltage of the second memory cell transistor is equal to or greater than the first voltage, and the control circuit is configured to supply a voltage equal to or less than the first voltage to the first word line.