Nonvolatile Memory Word Line Control for Read Speed and Power
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices face challenges in achieving high-speed read operations while minimizing power consumption, particularly in reducing the charging and discharging of word lines during read operations.
Innovation Solution
The nonvolatile semiconductor memory device employs a configuration where a word line commonly connects multiple memory strings, and during read operations, the select transistors of one group are turned off while the other group is turned on, reducing the amount of charging and discharging of the word line, thereby enhancing read speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the word line is charged and discharged during each read operation, then the memory strings can be selected and accessed, but the read operation speed is reduced and power consumption increases
Solution Approach 1:
The memory strings are divided into two groups (first group and second group) with different select transistor configurations. During read operations, only one group is activated at a time, allowing the word line to maintain its charged state for multiple consecutive read operations on the same group, thereby reducing repeated charging/discharging cycles and improving read speed while lowering power consumption
Solution Approach 2:
The word line is charged in advance before a series of read operations on a particular group of memory strings. By maintaining this pre-charged state throughout the sequence of reads on the same group, the system eliminates the need to recharge the word line between each read operation, thus enhancing read speed and reducing energy consumption
2Measurement precision
If the word line potential is controlled and adjusted for each read operation, then accurate memory cell access is achieved, but potential control delay increases
Solution Approach 1:
Memory strings are segmented into two groups with distinct select transistor gate connections (first select gate and second select gate). This segmentation allows the system to maintain stable word line potential for extended periods when reading from the same group, reducing the frequency of potential adjustments and minimizing control delay while preserving access accuracy
Solution Approach 2:
The select transistor gates are dynamically controlled based on which group of memory strings is being accessed. By switching the select transistor states according to the active group, the system maintains optimal word line potential stability for the duration of sequential reads within the same group, thereby reducing potential control delay while ensuring accurate memory cell access
Data Source
AI summary
A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on.