3D Memory Word Line Isolation to Reduce Substrate Leakage
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Solution Overview
Problem
The traditional three-dimensional semiconductor memory device faces challenges in reliability due to the close proximity of the word line structure to the substrate, leading to parasitic capacitance and potential leak channels.
Innovation Solution
A method is proposed that involves forming a stack structure with alternately stacked dielectric and semiconductor layers, creating isolation structures to separate the stack into sub-stacks, forming word line openings with insulating structures between them and the substrate, and constructing word line structures within these openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the word line structure is positioned close to the substrate to reduce device area, then the integration density is improved, but parasitic capacitance increases and reliability deteriorates
Solution Approach 1:
The patent introduces a vertical dimension solution by forming an insulating structure between the word line structure and the substrate. This vertically separates the word line from the substrate while maintaining horizontal integration, thus reducing parasitic capacitance without increasing the device footprint area.
Solution Approach 2:
The patent introduces an insulating structure as an intermediary element positioned between the word line structure and the substrate. This intermediary layer electrically isolates the word line from the substrate, reducing parasitic capacitance and preventing leak channels while allowing close proximity for high density.
2Productivity
If the word line structure is positioned close to the substrate to increase integration density, then the device compactness is improved, but leak channels may form and reliability worsens
Solution Approach 1:
The insulating structure serves as a protective intermediary that completely isolates the word line structure from the substrate, blocking potential leak channels while enabling close spacing for high integration density.
Solution Approach 2:
The insulating structure is formed beforehand between the word line and substrate to prevent potential leak channels before they can form, providing proactive protection against reliability issues.
3Reliability
If the distance between word line structure and substrate is increased to reduce parasitic capacitance, then reliability is improved, but device area increases
Solution Approach 1:
The solution moves the separation from horizontal spacing to vertical spacing. The insulating structure creates vertical distance between the word line and substrate to reduce parasitic capacitance, while the horizontal footprint remains compact for high integration density.
Data Source
AI summary
A method for forming a semiconductor structure includes: forming a stack structure of alternately stacked dielectric layers and semiconductor layers on a substrate; forming isolation structures penetrating through the stack structure, and extending into the substrate, where the isolation structures separate the stack structure into sub-stack structures; forming word line openings extending along a third direction in each of the isolation structures, where a bottom surface of each of the word line openings is lower than a bottom surface of a semiconductor layer closest to the substrate, and each of the word line openings is located between one of the sub-stack structures and one of the isolation structures; forming an insulating structure between each of the word line openings and the substrate; and forming a word line structure in each of the word line openings.