Semiconductor Memory Word Line Select Transistors
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently controlling voltage pulses due to high wiring capacities between local and global word lines, leading to inadequate charge accumulation and operational issues during write and erase operations.
Innovation Solution
Incorporating word line select transistors between local and global word lines to reduce wiring capacity and enable faster voltage control, allowing for shorter pulse widths and improved operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct connection between local and global word lines is used, then wiring capacity increases, but voltage control speed decreases and charge accumulation occurs
Solution Approach 1:
Word line select transistors are introduced as intermediary components between local word lines and global word lines. These transistors act as switching elements that control the connection between the two wiring levels, enabling fast voltage control while preventing unwanted charge accumulation in the ferroelectric portions through selective switching.
2Productivity
If shorter pulse widths are used, then operational efficiency improves, but charge accumulation in ferroelectric portions occurs
Solution Approach 1:
The word line select transistors provide feedback control mechanism by selectively connecting or disconnecting local word lines from global word lines based on operational requirements. This feedback control enables precise management of voltage pulse delivery, achieving short pulse widths for high efficiency while preventing charge accumulation through controlled disconnection when needed.
Data Source
AI summary
A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.