Multi-level Nonvolatile Memory Word Line Setup Time Control
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Solution Overview
Problem
In multi-level nonvolatile semiconductor memory, the increased packing density of memory cell arrays leads to prolonged setup times for word lines due to higher wiring resistance and parasitic capacitance, which slows down the read operation, especially when storing multiple data levels.
Innovation Solution
A multi-level nonvolatile semiconductor memory system that adjusts the setup time of word lines based on the value of the selected read potential, shortening the time it takes for the potential to change from a non-selected to a selected read potential, thereby improving read operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the packing density of memory cell array is increased, then the storage capacity is improved, but the wiring resistance of word lines increases and parasitic capacitance between word lines increases, causing prolonged setup time
Solution Approach 1:
The patent applies dynamics by making the setup time variable rather than fixed. The control circuit dynamically adjusts the setup time of word lines based on the selected read potential value. When a higher read potential is selected, the setup time is shortened; when a lower read potential is selected, the setup time is extended. This dynamic adjustment optimizes the trade-off between storage capacity and read operation speed under different operating conditions.
Solution Approach 2:
The patent changes the parameter of setup time based on the read potential value. The control circuit monitors which read potential is currently selected and adjusts the word line setup time accordingly. This parameter change allows the system to adapt to different read operations, shortening setup time when higher potentials are used (which naturally charge word lines faster) and extending it when lower potentials are used, thereby maintaining optimal performance across all read operations.
2Quantity of substance
If the packing density of memory cell array is increased, then the storage capacity is improved, but the word lines become thinner, narrower, and longer, increasing wiring resistance
Solution Approach 1:
The patent compensates for increased wiring resistance by dynamically adjusting the setup time parameter. When higher read potentials are selected, the inherent faster charging effect (despite high resistance) is exploited by shortening setup time. When lower read potentials are selected, the slower charging due to high resistance is compensated by extending setup time, ensuring sufficient time for proper charging regardless of the resistance issues caused by high packing density.
3Quantity of substance
If the distances between word lines become narrower, then the packing density is improved, but parasitic capacitance between word lines increases, causing prolonged setup time
Solution Approach 1:
The patent addresses the capacitive coupling issue by dynamically adjusting setup time based on read potential selection. The control circuit recognizes that higher read potentials overcome parasitic capacitance effects more effectively and faster, so it shortens setup time in those cases. For lower read potentials where capacitive coupling has a more pronounced delaying effect, the setup time is extended to ensure proper charging completion.
4Device complexity
If a fixed setup time is used for all read potentials, then the control is simplified, but the read operation speed is limited by the longest setup time required
Solution Approach 1:
The patent implements dynamic setup time adjustment based on the selected read potential, achieving a balance between control complexity and read operation speed. The control circuit adds minimal complexity by monitoring the read potential selection and adjusting setup time accordingly. This allows the system to use shorter setup times for higher potentials (improving speed) while maintaining sufficient setup time for lower potentials (ensuring reliability), thereby optimizing overall read operation speed without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a faster read operation by dynamically adjusting the setup time of word lines in proportion to the selected read potential, reducing the overall time required for the potential to settle, thus enhancing the performance of multi-level nonvolatile semiconductor memory systems.
Implementation Method 1
word lines in one cell unit become thinner, narrower, and longer, increasing wiring resistance
Implementation Method 2
the distances between the word lines become narrower, increasing parasitic capacitance
Data Source
AI summary
A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a selected word line which is connected to a selected memory cell as a target of a reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which changes a set up term of the selected word line and the non-selected word line based on a value of the selected read potential, wherein the value of the selected read potential is selected from two or more potentials.