Semiconductor Memory Device Word Line Sharing Architecture
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating multiple memory cell arrays while minimizing the circuit scale of the row decoder and reducing the influence of write disturbance, which can lead to erroneous readings and reduced reliability.
Innovation Solution
The semiconductor memory device employs a configuration where some word lines are shared across multiple array chips, with both shared and individual word lines, allowing for controlled voltage application during write operations to minimize write disturbance and reduce the circuit scale of the row decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cell arrays are integrated in the semiconductor memory device, then the storage capacity is improved, but the circuit scale of the row decoder increases
Solution Approach 1:
The row decoder is segmented into multiple independent row decoders, each responsible for decoding a specific subset of word lines. This allows the decoding function to be distributed across multiple arrays, reducing the complexity of any single row decoder while maintaining the ability to address all memory cells in the integrated arrays.
Solution Approach 2:
Multiple row decoders are designed with identical or similar circuit structures, allowing them to perform the same decoding function for different arrays. This universality reduces design complexity and allows for modular integration, where the same decoder circuit can be reused across multiple arrays with minimal modification.
2Speed
If write operations are performed on memory cell arrays, then data writing speed is improved, but write disturbance affects adjacent cells causing erroneous readings
Solution Approach 1:
Different voltage levels are applied to different word lines during write operations based on their specific function and position. Word lines that are not selected for the write operation receive different voltage levels compared to the selected word line, thereby suppressing write disturbance in adjacent cells while maintaining efficient write speed to the target cells.
Solution Approach 2:
Before performing a write operation, the non-selected word lines are pre-charged to appropriate voltage levels that prevent unwanted charge injection into the floating gate of adjacent memory cells. This preliminary action counteracts the potential write disturbance effect before it can occur, ensuring data integrity in cells that are not the target of the write operation.
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a first chip, a second chip, and third chip. The first chip includes a first pillar including a first memory cell and a second memory cell coupled in series. The second chip includes a second pillar including a third memory cell and a fourth memory cell coupled in series. The third chip includes a row decoder to which a first word line, a second word line, and a third word line are coupled. The first word line is coupled to a gate of the first memory cell. The second word line is coupled to a gate of the third memory cell. The third word line is coupled to gates of the second memory cell and the fourth memory cell.