Semiconductor Memory Word Line Smart Refresh Control

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Solution Overview

Problem

As semiconductor memory devices integrate more densely, the reduced interval between word lines leads to coupling effects, increasing the risk of data loss, necessitating more frequent refresh operations that deteriorate device efficiency.

Innovation Solution

A semiconductor memory device with a refresh control unit that performs smart refresh operations on word lines with different address intervals, using a combination of normal and redundancy word lines, and smart mode signals to optimize refresh operations based on target addresses, thereby reducing data loss and improving efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the degree of integration of semiconductor memory devices is increased, then the density of memory cells is improved, but the coupling effect between adjacent word lines increases causing data loss

Engineering Contradiction:
Improvememory cell densityVSAvoiddata retention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the refresh operation into multiple groups based on address intervals. Instead of treating all word lines uniformly, it divides them into different segments (first group with first address interval, second group with second address interval) that can be refreshed with different frequencies, allowing selective refresh of affected areas while reducing overall refresh burden

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by identifying specific word lines that are susceptible to coupling effects (those adjacent to active word lines) and applying targeted refresh operations to these local areas. The refresh control unit selectively refreshes word lines based on their proximity to active word lines, rather than uniformly refreshing all word lines, thus addressing the local coupling problem without global overhead

Inventive Principle:
Principle #3Local quality

2Reliability

If the number of refresh operations is increased to prevent data loss, then data retention is improved, but the operation efficiency of the semiconductor memory device deteriorates

Engineering Contradiction:
Improvedata retentionVSAvoidoperation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements partial action by performing refresh operations only on specific word lines that are susceptible to coupling effects, rather than refreshing all word lines. The refresh control unit determines which word lines need refreshing based on address intervals and active word line patterns, applying refresh operations partially to the most affected areas while skipping others, thus reducing total refresh operations and improving efficiency

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the parameter of refresh frequency by implementing multiple address intervals (first address interval and second address interval) with different refresh frequencies. Word lines are refreshed at different rates based on their vulnerability to coupling effects, allowing the system to optimize between data retention and operation efficiency by adjusting refresh parameters dynamically

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9627096B2Semiconductor memory device
Publication Date: 2017.04.18 MIMIRIP LLC
  • US9627096B2 patent drawing
  • US9627096B2 patent drawing
  • US9627096B2 patent drawing

AI summary

A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.