Memory System Verify Operations for Odd and Even Word Lines
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Solution Overview
Problem
Existing memory systems face challenges in improving the accuracy of read and write operations in semiconductor memory devices, particularly in managing over-erased cells and maintaining precise threshold voltage distributions.
Innovation Solution
A memory system is designed with a specific configuration that includes multiple word lines, memory pillars, and a control circuit. This configuration allows for precise program and verify operations, including preliminary program operations with varying voltages, to address over-erased cells and narrow the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If verify operations are performed on both odd and even word lines, then the accuracy of read and write operations is improved, but the device complexity increases
Solution Approach 1:
The verify operation is segmented into two distinct phases: a first verify operation for even word lines and a second verify operation for odd word lines. This segmentation allows the system to manage the complexity of dual-word-line verification by dividing it into sequential, manageable steps, each handling a specific subset of word lines with dedicated voltage application and sensing procedures.
Solution Approach 2:
The first verify operation on even word lines is performed as a preliminary action before the second verify operation on odd word lines. This preliminary verification ensures that even word lines are properly programmed and verified before proceeding to odd word lines, maintaining data integrity while organizing the complex verification process into a structured sequence.
2Manufacturing precision
If preliminary program operations with varying voltages are performed, then the threshold voltage distribution is narrowed, but the loss of time increases
Solution Approach 1:
The program operation employs periodic voltage variations with multiple stages: an initial program voltage for first memory cells, followed by a second program voltage for second memory cells, and subsequent periodic voltage adjustments. This periodic action narrows the threshold voltage distribution by systematically addressing different cell groups with optimized voltages, achieving precise voltage control while managing the time required through structured repetition.
Solution Approach 2:
The system changes voltage parameters dynamically during the program operation, switching between different voltage levels (first program voltage, second program voltage) and adjusting verification voltages based on the specific word line being processed. These parameter changes enable precise control over the threshold voltage distribution, narrowing it by adapting voltage conditions to the specific needs of different memory cell groups.
3Reliability
If over-erased cells are managed through multiple program operations, then the reliability is improved, but the productivity decreases
Solution Approach 1:
The system performs preliminary program operations on memory cells before final verification, identifying and addressing over-erased cells in advance. This preliminary action includes initial programming, verification, and conditional re-programming of cells that fail verification, ensuring that reliability issues are resolved before the memory device is considered ready, thus maintaining high reliability while managing throughput.
Solution Approach 2:
The verify operation provides feedback on the state of memory cells, allowing the system to identify over-erased cells and apply corrective program operations only where needed. This feedback mechanism ensures that reliability is improved by targeting specific problematic cells rather than uniformly re-programming all cells, thereby maintaining productivity while enhancing data storage reliability.
Data Source
AI summary
A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.