Semiconductor Memory Word Line Voltage Control for Cell Disturbance
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Solution Overview
Problem
In semiconductor memory devices, the high voltage applied to word lines can cause disturbances to adjacent cells, especially as chip sizes decrease, leading to increased interference between memory cells.
Innovation Solution
The implementation of power selection switches that control the deactivation voltage levels of word lines, allowing for different voltage levels such as ground voltage, first negative voltage, and second negative voltage to minimize interference between adjacent cells by individually managing the deactivation and activation states of word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to word line to enable transistor access to memory cell, then memory cell access is enabled, but disturbance to adjacent cell access transistor occurs
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their selection state. The selected word line receives high voltage for activation, while adjacent unselected word lines receive progressively lower voltage levels (first negative voltage, second negative voltage) to minimize disturbance. This localized voltage differentiation reduces coupling interference between adjacent cells while maintaining reliable access to the target memory cell.
Solution Approach 2:
The patent dynamically changes voltage parameters of word lines during the memory access operation. During the activation period, the selected word line is driven at a first voltage level while adjacent word lines are driven at a second voltage level. During deactivation, the selected word line transitions through intermediate voltage levels (third voltage level between first and second) before reaching the final off-voltage level. This parameter change approach ensures reliable cell access while minimizing disturbance to adjacent cells throughout the operation timeline.
2Area of stationary object
If chip size is reduced to decrease distance between adjacent cells, then device integration is improved, but disturbance between adjacent cells increases
Solution Approach 1:
The patent implements localized voltage control where each word line receives a voltage level appropriate to its functional state. By applying negative voltage levels specifically to unselected word lines, the patent creates electrical isolation zones that prevent interference propagation between closely spaced cells, enabling high-density integration without sacrificing signal integrity.
Solution Approach 2:
The patent applies negative voltage levels to unselected word lines before and during the activation of the selected word line. This preliminary anti-action creates a protective voltage barrier that prevents the high voltage signal on the selected word line from coupling into adjacent unselected word lines, thereby preventing disturbance before it can occur.
3Object-affected harmful factors
If deactivation voltage level of selected word line and off-voltage level of adjacent word line are controlled to have different voltage levels, then disturbance between word lines is reduced, but device complexity increases
Solution Approach 1:
The patent segments the voltage control function into multiple independent control paths. Power selection switches are introduced to separately control the deactivation voltage level of the selected word line and the off-voltage level of unselected word lines. This segmentation allows independent optimization of voltage levels for different word line states, reducing disturbance while maintaining manageable complexity through modular control architecture.
Solution Approach 2:
The patent introduces power selection switches as intermediary components between the voltage source and the word lines. These switches act as mediators that selectively connect different voltage levels to different word lines based on their selection state. This intermediary approach simplifies the overall control logic by providing clear separation between selected and unselected word line voltage management.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.