Semiconductor Memory Word Line Voltage Control
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Solution Overview
Problem
Conventional semiconductor memory devices face issues with voltage drops in channels and subsequent voltage rises during read, write, and verify operations, leading to threshold shifts and increased fail bits due to simultaneous voltage changes across all word lines and select gate lines.
Innovation Solution
The semiconductor memory device employs a control circuit to independently manage the fall timings and rates of word lines, ensuring charges exit to the bit line or well region without being cut off, by dividing word lines into groups and controlling their sequential fall, thereby maintaining memory cell transistors in a stable state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all word lines and select gate lines change voltage simultaneously during read, write, and verify operations, then operation speed is improved, but voltage drops in channels occur leading to threshold shifts and increased fail bits
Solution Approach 1:
The patent segments the word lines into multiple groups (first group, second group, third group) and controls their voltage changes independently. During read operations, the selected word line group changes voltage first while other groups maintain stable voltage. During write operations, word line groups change voltage sequentially rather than simultaneously. This segmentation prevents channel voltage drops and threshold shifts while maintaining operational speed.
2Reliability
If word lines are controlled to fall sequentially in groups, then threshold shifts are reduced and fail bits are minimized, but control circuit complexity increases
Solution Approach 1:
The control circuit is designed with segmented control capabilities for different word line groups. Each group can be controlled independently to change voltage at appropriate times. This segmentation allows the circuit to maintain simple control logic for each group while achieving complex overall control through coordinated group operations.
Solution Approach 2:
The control circuit implements periodic action by establishing specific timing sequences for voltage changes in different word line groups. During read operations, the selected group changes voltage at a specific time while other groups remain stable. During write operations, groups change voltage in a predetermined sequence. This periodic timing control reduces threshold shifts without requiring overly complex control logic.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, a first word line electrically coupled to the first memory cell, a second word line electrically coupled to the second memory cell, and a control circuit configured to supply voltages to the first word line and the second word line. In a read, the control circuit applies a first voltage to the first word line and a second voltage to the second word line, applies, after applying the first voltage to the first word line and the second voltage to the second word line, a third voltage lower than the first voltage and the second voltage to the second word line, and applies, after applying the third voltage to the second word line, the third voltage to the first word line.