Memory Device Word Line Voltage Control
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Solution Overview
Problem
Memory devices face performance degradation due to uncontrolled threshold voltage distribution in memory cells after an erase operation, primarily caused by improper voltage control during the erase process, leading to inefficiencies and errors in data reading.
Innovation Solution
A memory device design that reduces the voltage input to word lines from a first bias voltage to a second bias voltage during the erase operation, specifically controlling the voltage of different word lines at different times to minimize the coupling effect between word lines and the channel layer, thereby stabilizing the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a constant bias voltage is applied to all word lines during erase operation, then the erase operation can be simply controlled, but the threshold voltage distribution of memory cells deteriorates due to coupling effects
Solution Approach 1:
The patent divides the word lines into multiple groups (first word line group and second word line group) and applies different voltage control strategies to each group. During the erase operation, the first word line group voltage is reduced to a first erase voltage while the second word line group voltage is reduced to a second erase voltage at a different timing, segmenting the uniform voltage control into differentiated control to reduce coupling effects and improve threshold voltage distribution.
Solution Approach 2:
The patent implements dynamic voltage control where the voltages of different word line groups are changed at different timings during the erase operation. The peripheral circuit dynamically adjusts the voltage reduction timing for each word line group based on their positions, creating a time-dependent voltage profile that optimizes the erase operation and minimizes coupling effects between word lines and channel structures.
2Reliability
If the voltage of word lines is not reduced during erase operation, then the coupling component between word lines and channel layer remains high, but the threshold voltage distribution variation increases
Solution Approach 1:
The patent applies different voltage levels and reduction timings to different word line groups based on their local positions relative to the channel structures. The first word line group (closer to channel structures) has its voltage reduced to a first erase voltage, while the second word line group has its voltage reduced to a second erase voltage at different timing, creating localized voltage conditions that minimize coupling effects at each position and improve overall threshold voltage uniformity.
3Manufacturing precision
If different voltages are applied to different word line groups during erase operation, then the threshold voltage distribution is improved, but the control complexity increases
Solution Approach 1:
The patent implements a universal voltage control approach where multiple word line groups share the same peripheral circuit and voltage control mechanism, but with differentiated timing control. The same type of voltage signal is applied to different word line groups at different timings, achieving complex differential control through a unified control architecture that minimizes additional circuit complexity while maintaining precision.
Data Source
AI summary
A memory device includes a cell area including memory blocks, and a peripheral circuit area including peripheral circuits that execute an erase operation for each of the memory blocks. Each memory block includes word lines that are stacked on a substrate, channel structures penetrate through the word lines, and a source region that is disposed on the substrate and connected to the channel structures. During the erase operation in which an erase voltage is provided to the source region of a target memory block among the memory blocks, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time, and to reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first time.