Memory Error Correction Using Word and Page Parity
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Solution Overview
Problem
Traditional memory error correction schemes are burdensome in terms of overhead and power consumption, particularly in NOR Flash Memories, and are inadequate for memories with differing read and write operations.
Innovation Solution
A method for detecting and correcting errors in memory that involves determining word parity and page parity, allowing for error detection and correction during read operations, with reduced encoder/decoder complexities and parity overhead, using a parity matrix construct and Hamming encoding to share parity bits between error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction schemes are used with parity bits for each word, then error detection capability is improved, but overhead and power consumption increase substantially
Solution Approach 1:
The patent merges error detection and correction functions into a unified scheme. Instead of separate parity bits for detection and correction, the invention uses a single set of parity bits that serve both purposes simultaneously, reducing overhead while maintaining reliability.
Solution Approach 2:
The parity bits in the invention serve multiple functions: they detect errors, locate errors, and enable correction. This multi-functionality eliminates the need for separate detection and correction mechanisms, reducing the overall overhead burden on the memory system.
2Reliability
If traditional error correction schemes are used with parity bits for each word, then error detection capability is improved, but power consumption increases
Solution Approach 1:
The patent combines error detection and correction operations into a single process that occurs during normal read operations. By merging these functions, the system avoids additional power-consuming separate detection and correction passes, reducing overall power consumption while maintaining error handling capability.
Solution Approach 2:
The error detection and correction is performed continuously during normal read operations rather than requiring separate dedicated operations. This continuous integration allows the system to maintain error protection without the additional power overhead of separate error handling cycles.
3Measurement precision
If all words and parity bits are read for error detection, then error detection accuracy is improved, but read performance degrades
Solution Approach 1:
The patent extracts the error detection and correction functionality to be performed on-demand during read operations rather than requiring all words and parity bits to be read for every access. This selective approach maintains error detection accuracy for accessed data while avoiding the performance penalty of reading entire pages unnecessarily.
Solution Approach 2:
The parity bits are pre-calculated and stored alongside the data words during write operations. This preliminary preparation allows for rapid error detection and correction during read operations without requiring additional processing time, thus maintaining read performance while ensuring error detection accuracy.
4Reliability
If traditional schemes are used for memories with differing read and write operations, then error correction is provided, but the scheme is inadequate for such memories
Solution Approach 1:
The patent implements a dynamic error handling scheme that adapts to different memory operation modes. The system can adjust its error detection and correction behavior based on whether the operation is a read or write, making it suitable for memories like NOR Flash that have fundamentally different read and write characteristics.
Solution Approach 2:
The invention changes operational parameters based on the type of memory operation being performed. For write operations, parity bits are calculated and stored; for read operations, the same parity bits are used for error detection and correction. This parameter adaptation allows the single scheme to handle differing read and write operations effectively.
Data Source
AI summary
A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.