3D Memory Word-Line Air Gaps for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in reducing parasitic capacitance between word lines, which limits the operational frequency and efficiency of memory devices.
Innovation Solution
The implementation of air gaps between word lines in a 3D memory array, formed by removing sacrificial material and sealing the ends with a dielectric material, reduces parasitic capacitance and enhances device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If dielectric material is used between word lines, then insulation is provided, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the dielectric material from between the word lines by removing sacrificial material, creating air gaps instead. This eliminates the source of parasitic capacitance while maintaining the necessary insulation through the air medium and sealing structure.
Solution Approach 2:
The patent uses air (an inert atmosphere) as the medium between word lines to replace dielectric material. The air gaps provide insulation with minimal parasitic capacitance, and the ends are sealed with dielectric material to maintain the inert environment and prevent contamination.
2Object-affected harmful factors
If air gaps are formed between word lines, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial material layers between word lines during the manufacturing process before final assembly. These sacrificial layers are later removed to create air gaps, allowing the complex structure to be built using standard deposition and etching processes rather than requiring direct air gap formation.
Solution Approach 2:
The patent uses sacrificial material as an intermediary substance that temporarily occupies the space between word lines during manufacturing. This mediator allows standard fabrication processes to be used, and it is subsequently removed to create the desired air gaps, simplifying the overall manufacturing approach.
3Quantity of substance
If word lines are placed closer together, then memory density is increased, but parasitic capacitance between word lines increases
Solution Approach 1:
By extracting dielectric material and replacing it with air gaps, the patent enables word lines to be placed closer together without the parasitic capacitance penalty that would normally accompany reduced spacing. The air medium provides insulation with minimal capacitive coupling.
Solution Approach 2:
The patent changes the dielectric parameter between word lines from high-k dielectric material to air (k≈1), fundamentally altering the capacitance characteristics. This parameter change allows for reduced word line spacing while maintaining low parasitic capacitance, thereby increasing memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher-frequency operation and improved device efficiency by minimizing parasitic capacitance and noise, particularly in high-frequency applications.
Implementation Method 1
reduces parasitic capacitance between the word lines
Implementation Method 2
sealing the ends of the air gaps with a dielectric material
Data Source
AI summary
A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.